Re: [edk2] [PATCH edk2-platforms 00/12] Hisilicon/D0x: Switch to generic PciHostBridge

[gary guo]

Sure. A little busy these days; I'll do that ASAP.

Thanks,

Heyi

On Thu, Jun 07, 2018 at 01:11:59PM +0200, Ard Biesheuvel wrote:
> On 17 April 2018 at 03:20, Guo Heyi  wrote:
> > Hi Ard,
> >
> > I tested mm -io on D05, for root bridge 4 with CPU IO address starting from
> > 0x8_abff, and it worked; both mm -io 0x8abff and mm 0x8abff 
> > provided
> > the same output. It seems there is no other limit for 64bit IO address 
> > after you
> > fixed the issue in EFI shell mm command.
> >
> 
> OK, so I think this is fine after all, even if my uneasy feeling
> hasn't gone away :-)
> 
> Could you please resend the latest rebased version of the patches?
> (and include the ATU fix as well)
> 
> 
> > On Mon, Apr 16, 2018 at 09:57:09PM +0800, Guo Heyi wrote:
> >> Thanks, I will test mm command and let you know the result.
> >>
> >> Regards,
> >>
> >> Heyi
> >>
> >> On Fri, Apr 13, 2018 at 09:19:53AM +0200, Ard Biesheuvel wrote:
> >> > On 13 April 2018 at 04:05, Guo Heyi  wrote:
> >> > > Hi Ard,
> >> > >
> >> > > Any comments?
> >> > >
> >> >
> >> > Apologies for the delay. I have been travelling and am behind on email.
> >> >
> >> > > Anyway we can modify the code if you insist on using an intermediate 
> >> > > CPU IO
> >> > > address space.
> >> > >
> >> >
> >> > I have not made up my mind yet, to be honest. I agree there is a
> >> > certain elegance to merging both translations, but I am concerned that
> >> > existing EDK2 code may deal poorly with I/O addresses that require
> >> > more than 32 bits to express.
> >> >
> >> > Did you try the mm command in the shell for instance? As you know, I
> >> > recently removed an artificial address range limit there, but I wonder
> >> > if it uses 64-bit variables for I/O ports.
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Re: [edk2] [RFC] MdeModulePkg/PciHostBridge: Add address translation support

[gary guo]

On Tue, Jan 02, 2018 at 03:56:14PM +0800, Ni, Ruiyu wrote:
> On 12/26/2017 2:50 PM, Guo Heyi wrote:
> > Hi Ard, Ray,
> > 
> > Have we come to the final conclusion? Or are we still waiting for more 
> > comments on this?
> 
> Heyi,
> I think you can send out a draft version of changes for better
> understanding.

Sure, we can do that.
Thanks,

Gary

> 
> > 
> > Thanks,
> > 
> > Gary
> > 
> > On Thu, Dec 21, 2017 at 10:07:51AM +, Ard Biesheuvel wrote:
> > > On 21 December 2017 at 09:59, Ni, Ruiyu <ruiyu...@intel.com> wrote:
> > > > On 12/21/2017 5:52 PM, Ard Biesheuvel wrote:
> > > > > 
> > > > > On 21 December 2017 at 09:48, Ni, Ruiyu <ruiyu...@intel.com> wrote:
> > > > > > 
> > > > > > On 12/21/2017 5:14 PM, Guo Heyi wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > On Thu, Dec 21, 2017 at 08:32:37AM +, Ard Biesheuvel wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On 21 December 2017 at 08:27, Guo Heyi <heyi@linaro.org> 
> > > > > > > > wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On Wed, Dec 20, 2017 at 03:26:45PM +, Ard Biesheuvel 
> > > > > > > > > wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > On 20 December 2017 at 15:17, gary guo 
> > > > > > > > > > <heyi@linaro.org> wrote:
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > On Wed, Dec 20, 2017 at 09:13:58AM +, Ard Biesheuvel 
> > > > > > > > > > > wrote:
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > Hi Heyi,
> > > > > > > > > > > > 
> > > > > > > > > > > > On 20 December 2017 at 08:21, Heyi Guo 
> > > > > > > > > > > > <heyi@linaro.org> wrote:
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > PCIe on some ARM platforms requires address 
> > > > > > > > > > > > > translation, not only
> > > > > > > > > > > > > for
> > > > > > > > > > > > > legacy IO access, but also for 32bit memory BAR 
> > > > > > > > > > > > > access as well.
> > > > > > > > > > > > > There
> > > > > > > > > > > > > will be "Address Translation Unit" or something 
> > > > > > > > > > > > > similar in PCI
> > > > > > > > > > > > > host
> > > > > > > > > > > > > bridges to translation CPU address to PCI address and 
> > > > > > > > > > > > > vice versa.
> > > > > > > > > > > > > So
> > > > > > > > > > > > > we think it may be useful to add address translation 
> > > > > > > > > > > > > support to
> > > > > > > > > > > > > the
> > > > > > > > > > > > > generic PCI host bridge driver.
> > > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > I agree. While unusual on a PC, it is quite common on 
> > > > > > > > > > > > other
> > > > > > > > > > > > architectures to have more complex non 1:1 topologies, 
> > > > > > > > > > > > which
> > > > > > > > > > > > currently
> > > > > > > > > > > > require a forked PciHostBridgeDxe driver with local 
> > > > > > > > > > > > changes
> > > > > > > > > > > > applied.
> > > > > > > &