Re: [edk2] [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller
> -Original Message- > From: Leif Lindholm > Sent: Wednesday, December 19, 2018 12:16 AM > To: Meenakshi Aggarwal > Cc: ard.biesheu...@linaro.org; michael.d.kin...@intel.com; edk2- > de...@lists.01.org; Udit Kumar ; Varun Sethi > > Subject: Re: [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC > controller > > On Wed, Nov 28, 2018 at 08:31:25PM +0530, Meenakshi Aggarwal wrote: > > This header file contain IFC controller timing structure, chip select > > enum and other IFC macros. > > Please expand the IFC acronym here (like is done in file header below). > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Meenakshi Aggarwal > > --- > > Silicon/NXP/Include/Ifc.h | 423 > > ++ > > Please Update at least filename Ifc.h->NxpIfc.h > > > 1 file changed, 423 insertions(+) > > create mode 100644 Silicon/NXP/Include/Ifc.h > > > > diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h new > > file mode 100644 index 000..6babb22 > > --- /dev/null > > +++ b/Silicon/NXP/Include/Ifc.h > > @@ -0,0 +1,423 @@ > > +/** @Ifc.h > > + > > + The integrated flash controller (IFC) is used to interface with > > + external asynchronous NAND flash, asynchronous NOR flash, SRAM, generic > ASIC memories and EPROM. > > + > > + Copyright 2017 NXP > > + > > + This program and the accompanying materials are licensed and made > > + available under the terms and conditions of the BSD License which > > + accompanies this distribution. The full text of the license may be > > + found at > > + > > + https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fop > > + ensource.org%2Flicenses%2Fbsd- > license.php&data=02%7C01%7Cmeenaks > > + > hi.aggarwal%40nxp.com%7Cf5720bda0a8c4ab0dd6708d6651904fb%7C686ea1d > 3b > > + > c2b4c6fa92cd99c5c301635%7C0%7C0%7C636807555468004917&sdata=df > OWZ > > + Z2yXCKi55Cl94sAEGYx739%2FXCiK1yX3Wm6lTow%3D&reserved=0 > > + > > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > > + BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > EITHER EXPRESS OR IMPLIED. > > + > > +**/ > > + > > +#ifndef __IFC_H__ > > +#define __IFC_H__ > > Please add NXP_ prefix. > > (I am less concerned about the actual defines below.) > > > + > > +#include > > Is BaseLib.h really used by this file? Yes, it is needed for HighBitSet32() used in this file. > If not, please drop it. > > > +#include > > + > > +#define IFC_BANK_COUNT4 > > + > > +#define IFC_CSPR_REG_LEN 148 > > +#define IFC_AMASK_REG_LEN 144 > > +#define IFC_CSOR_REG_LEN 144 > > +#define IFC_FTIM_REG_LEN 576 > > + > > +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \ > > + IFC_BANK_COUNT > > + > > +#define IFC_AMASK_USED_LENsizeof (IFC_AMASK) * \ > > + IFC_BANK_COUNT > > + > > +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \ > > + IFC_BANK_COUNT > > + > > +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \ > > + IFC_BANK_COUNT > > + > > +/* List of commands */ > > +#define IFC_NAND_CMD_RESET0xFF > > +#define IFC_NAND_CMD_READID 0x90 > > +#define IFC_NAND_CMD_STATUS 0x70 > > +#define IFC_NAND_CMD_READ00x00 > > +#define IFC_NAND_CMD_READSTART0x30 > > +#define IFC_NAND_CMD_ERASE1 0x60 > > +#define IFC_NAND_CMD_ERASE2 0xD0 > > +#define IFC_NAND_CMD_SEQIN0x80 > > +#define IFC_NAND_CMD_PAGEPROG 0x10 > > +#define MAX_RETRY_COUNT 15 > > + > > + > > +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x8000 > > + > > +/* > > + * NAND Event and Error Status Register (NAND_EVTER_STAT) */ > > + > > +/* Operation Complete */ > > +#define IFC_NAND_EVTER_STAT_OPC 0x8000 > > + > > +/* Flash Timeout Error */ > > +#define IFC_NAND_EVTER_STAT_FTOER 0x0800 > > + > > +/* Write Protect Error */ > > +#define IFC_NAND_EVTER_STAT_WPER0x0400 > > + > > +/* ECC Error */ > > +#define IFC_NAND_EVTER_STAT_ECCER 0x0200 > > + > > +/* > > + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) > > +*/ > > + > > +/* NAND Machine specific opcodes OP0-OP14*/ > > +#define IFC_NAND_FIR0_OP0 0xFC00 > > +#define IFC_NAND_FIR0_OP0_SHIFT 26 > > +#define IFC_NAND_FIR0_OP1 0x03F0 > > +#define IFC_NAND_FIR0_OP1_SHIFT 20 > > +#define IFC_NAND_FIR0_OP2 0x000FC000 > > +#define IFC_NAND_FIR0_OP2_SHIFT 14 > > +#define IFC_NAND_FIR0_OP3 0x3F00 > > +#define IFC_NAND_FIR0_OP3_SHIFT 8 > > +#define IFC_NAND_FIR0_OP4 0x00FC > > +#define IFC_NAND_FIR0_OP4_SHIFT 2 > > +#define IFC_NAND_FIR1_OP5 0xFC00 > > +#define IFC_NAND_FIR1_OP5_SHIFT 26 > > +#define IFC_NAND_FIR1_OP6 0x03F0 > > +#define IFC_NAND_FIR1_OP6_SHIFT 20 > > +#define IFC_NAND_FIR1_OP7 0x000FC000 > > +#define IFC_NAND_FIR1_OP7_
Re: [edk2] [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller
On Wed, Nov 28, 2018 at 08:31:25PM +0530, Meenakshi Aggarwal wrote: > This header file contain IFC controller timing structure, > chip select enum and other IFC macros. Please expand the IFC acronym here (like is done in file header below). > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Meenakshi Aggarwal > --- > Silicon/NXP/Include/Ifc.h | 423 > ++ Please Update at least filename Ifc.h->NxpIfc.h > 1 file changed, 423 insertions(+) > create mode 100644 Silicon/NXP/Include/Ifc.h > > diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h > new file mode 100644 > index 000..6babb22 > --- /dev/null > +++ b/Silicon/NXP/Include/Ifc.h > @@ -0,0 +1,423 @@ > +/** @Ifc.h > + > + The integrated flash controller (IFC) is used to interface with external > asynchronous > + NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM. > + > + Copyright 2017 NXP > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD > License > + which accompanies this distribution. The full text of the license may be > found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > IMPLIED. > + > +**/ > + > +#ifndef __IFC_H__ > +#define __IFC_H__ Please add NXP_ prefix. (I am less concerned about the actual defines below.) > + > +#include Is BaseLib.h really used by this file? If not, please drop it. > +#include > + > +#define IFC_BANK_COUNT4 > + > +#define IFC_CSPR_REG_LEN 148 > +#define IFC_AMASK_REG_LEN 144 > +#define IFC_CSOR_REG_LEN 144 > +#define IFC_FTIM_REG_LEN 576 > + > +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \ > + IFC_BANK_COUNT > + > +#define IFC_AMASK_USED_LENsizeof (IFC_AMASK) * \ > + IFC_BANK_COUNT > + > +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \ > + IFC_BANK_COUNT > + > +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \ > + IFC_BANK_COUNT > + > +/* List of commands */ > +#define IFC_NAND_CMD_RESET0xFF > +#define IFC_NAND_CMD_READID 0x90 > +#define IFC_NAND_CMD_STATUS 0x70 > +#define IFC_NAND_CMD_READ00x00 > +#define IFC_NAND_CMD_READSTART0x30 > +#define IFC_NAND_CMD_ERASE1 0x60 > +#define IFC_NAND_CMD_ERASE2 0xD0 > +#define IFC_NAND_CMD_SEQIN0x80 > +#define IFC_NAND_CMD_PAGEPROG 0x10 > +#define MAX_RETRY_COUNT 15 > + > + > +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x8000 > + > +/* > + * NAND Event and Error Status Register (NAND_EVTER_STAT) > + */ > + > +/* Operation Complete */ > +#define IFC_NAND_EVTER_STAT_OPC 0x8000 > + > +/* Flash Timeout Error */ > +#define IFC_NAND_EVTER_STAT_FTOER 0x0800 > + > +/* Write Protect Error */ > +#define IFC_NAND_EVTER_STAT_WPER0x0400 > + > +/* ECC Error */ > +#define IFC_NAND_EVTER_STAT_ECCER 0x0200 > + > +/* > + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) > + */ > + > +/* NAND Machine specific opcodes OP0-OP14*/ > +#define IFC_NAND_FIR0_OP0 0xFC00 > +#define IFC_NAND_FIR0_OP0_SHIFT 26 > +#define IFC_NAND_FIR0_OP1 0x03F0 > +#define IFC_NAND_FIR0_OP1_SHIFT 20 > +#define IFC_NAND_FIR0_OP2 0x000FC000 > +#define IFC_NAND_FIR0_OP2_SHIFT 14 > +#define IFC_NAND_FIR0_OP3 0x3F00 > +#define IFC_NAND_FIR0_OP3_SHIFT 8 > +#define IFC_NAND_FIR0_OP4 0x00FC > +#define IFC_NAND_FIR0_OP4_SHIFT 2 > +#define IFC_NAND_FIR1_OP5 0xFC00 > +#define IFC_NAND_FIR1_OP5_SHIFT 26 > +#define IFC_NAND_FIR1_OP6 0x03F0 > +#define IFC_NAND_FIR1_OP6_SHIFT 20 > +#define IFC_NAND_FIR1_OP7 0x000FC000 > +#define IFC_NAND_FIR1_OP7_SHIFT 14 > +#define IFC_NAND_FIR1_OP8 0x3F00 > +#define IFC_NAND_FIR1_OP8_SHIFT 8 > +#define IFC_NAND_FIR1_OP9 0x00FC > +#define IFC_NAND_FIR1_OP9_SHIFT 2 > +#define IFC_NAND_FIR2_OP10 0xFC00 > +#define IFC_NAND_FIR2_OP10_SHIFT26 > +#define IFC_NAND_FIR2_OP11 0x03F0 > +#define IFC_NAND_FIR2_OP11_SHIFT20 > +#define IFC_NAND_FIR2_OP12 0x000FC000 > +#define IFC_NAND_FIR2_OP12_SHIFT14 > +#define IFC_NAND_FIR2_OP13 0x3F00 > +#define IFC_NAND_FIR2_OP13_SHIFT8 > +#define IFC_NAND_FIR2_OP14 0x00FC > +#define IFC_NAND_FIR2_OP14_SHIFT2 > + > +/* > + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) > + */ > + > +/* General purpose FCM flash command bytes CMD0-CMD7 */ > +#define IFC_NAND_FCR0_CMD0 0xFF00 > +#define IFC_NAND_FCR0_CMD0_SHIFT24 > +#define IFC_NAND_FCR0_CMD1 0x00FF > +#define IFC_N
[edk2] [PATCH edk2-platforms 11/41] IFC : Add Header file for IFC controller
This header file contain IFC controller timing structure, chip select enum and other IFC macros. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Meenakshi Aggarwal --- Silicon/NXP/Include/Ifc.h | 423 ++ 1 file changed, 423 insertions(+) create mode 100644 Silicon/NXP/Include/Ifc.h diff --git a/Silicon/NXP/Include/Ifc.h b/Silicon/NXP/Include/Ifc.h new file mode 100644 index 000..6babb22 --- /dev/null +++ b/Silicon/NXP/Include/Ifc.h @@ -0,0 +1,423 @@ +/** @Ifc.h + + The integrated flash controller (IFC) is used to interface with external asynchronous + NAND flash, asynchronous NOR flash, SRAM, generic ASIC memories and EPROM. + + Copyright 2017 NXP + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __IFC_H__ +#define __IFC_H__ + +#include +#include + +#define IFC_BANK_COUNT4 + +#define IFC_CSPR_REG_LEN 148 +#define IFC_AMASK_REG_LEN 144 +#define IFC_CSOR_REG_LEN 144 +#define IFC_FTIM_REG_LEN 576 + +#define IFC_CSPR_USED_LEN sizeof (IFC_CSPR) * \ + IFC_BANK_COUNT + +#define IFC_AMASK_USED_LENsizeof (IFC_AMASK) * \ + IFC_BANK_COUNT + +#define IFC_CSOR_USED_LEN sizeof (IFC_CSOR) * \ + IFC_BANK_COUNT + +#define IFC_FTIM_USED_LEN sizeof (IFC_FTIM) * \ + IFC_BANK_COUNT + +/* List of commands */ +#define IFC_NAND_CMD_RESET0xFF +#define IFC_NAND_CMD_READID 0x90 +#define IFC_NAND_CMD_STATUS 0x70 +#define IFC_NAND_CMD_READ00x00 +#define IFC_NAND_CMD_READSTART0x30 +#define IFC_NAND_CMD_ERASE1 0x60 +#define IFC_NAND_CMD_ERASE2 0xD0 +#define IFC_NAND_CMD_SEQIN0x80 +#define IFC_NAND_CMD_PAGEPROG 0x10 +#define MAX_RETRY_COUNT 15 + + +#define IFC_NAND_SEQ_STRT_FIR_STRT 0x8000 + +/* + * NAND Event and Error Status Register (NAND_EVTER_STAT) + */ + +/* Operation Complete */ +#define IFC_NAND_EVTER_STAT_OPC 0x8000 + +/* Flash Timeout Error */ +#define IFC_NAND_EVTER_STAT_FTOER 0x0800 + +/* Write Protect Error */ +#define IFC_NAND_EVTER_STAT_WPER0x0400 + +/* ECC Error */ +#define IFC_NAND_EVTER_STAT_ECCER 0x0200 + +/* + * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2) + */ + +/* NAND Machine specific opcodes OP0-OP14*/ +#define IFC_NAND_FIR0_OP0 0xFC00 +#define IFC_NAND_FIR0_OP0_SHIFT 26 +#define IFC_NAND_FIR0_OP1 0x03F0 +#define IFC_NAND_FIR0_OP1_SHIFT 20 +#define IFC_NAND_FIR0_OP2 0x000FC000 +#define IFC_NAND_FIR0_OP2_SHIFT 14 +#define IFC_NAND_FIR0_OP3 0x3F00 +#define IFC_NAND_FIR0_OP3_SHIFT 8 +#define IFC_NAND_FIR0_OP4 0x00FC +#define IFC_NAND_FIR0_OP4_SHIFT 2 +#define IFC_NAND_FIR1_OP5 0xFC00 +#define IFC_NAND_FIR1_OP5_SHIFT 26 +#define IFC_NAND_FIR1_OP6 0x03F0 +#define IFC_NAND_FIR1_OP6_SHIFT 20 +#define IFC_NAND_FIR1_OP7 0x000FC000 +#define IFC_NAND_FIR1_OP7_SHIFT 14 +#define IFC_NAND_FIR1_OP8 0x3F00 +#define IFC_NAND_FIR1_OP8_SHIFT 8 +#define IFC_NAND_FIR1_OP9 0x00FC +#define IFC_NAND_FIR1_OP9_SHIFT 2 +#define IFC_NAND_FIR2_OP10 0xFC00 +#define IFC_NAND_FIR2_OP10_SHIFT26 +#define IFC_NAND_FIR2_OP11 0x03F0 +#define IFC_NAND_FIR2_OP11_SHIFT20 +#define IFC_NAND_FIR2_OP12 0x000FC000 +#define IFC_NAND_FIR2_OP12_SHIFT14 +#define IFC_NAND_FIR2_OP13 0x3F00 +#define IFC_NAND_FIR2_OP13_SHIFT8 +#define IFC_NAND_FIR2_OP14 0x00FC +#define IFC_NAND_FIR2_OP14_SHIFT2 + +/* + * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1) + */ + +/* General purpose FCM flash command bytes CMD0-CMD7 */ +#define IFC_NAND_FCR0_CMD0 0xFF00 +#define IFC_NAND_FCR0_CMD0_SHIFT24 +#define IFC_NAND_FCR0_CMD1 0x00FF +#define IFC_NAND_FCR0_CMD1_SHIFT16 +#define IFC_NAND_FCR0_CMD2 0xFF00 +#define IFC_NAND_FCR0_CMD2_SHIFT8 +#define IFC_NAND_FCR0_CMD3 0x00FF +#define IFC_NAND_FCR0_CMD3_SHIFT0 +#define IFC_NAND_FCR1_CMD4 0xFF00 +#define IFC_NAND_FCR1_CMD4_SHIFT24 +#define IFC_NAND_FCR1_CMD5 0x00FF +#define IFC_NAND_FCR1_CMD5_SHIFT16 +#define IFC_NAND_FCR1_CMD6 0xFF00 +#define IFC_NAND_FCR1_CMD6_SHIFT8 +#define IFC_NAND_FCR1_CMD7 0x00FF +#define IFC_NAND_FCR1_CMD7_SHIFT0 + +/* Timing registers for NAND Flash */ + +#define IFC_FTIM0_NAND_TC
