Re: [edk2] [PATCH edk2-platforms 18/27] Silicon/NXP: Add i.MX6 Clock Library
On Fri, Sep 21, 2018 at 08:26:11AM +, Chris Co wrote:
> This adds support for managing clocks on NXP i.MX6 SoC. It will
> manipulate the Clock Gating registers (CCGR).
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Christopher Co
> Cc: Ard Biesheuvel
> Cc: Leif Lindholm
> Cc: Michael D Kinney
> ---
> Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c | 1876
>
> Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwrLib.inf| 46 +
> Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr_private.h | 221 +++
> 3 files changed, 2143 insertions(+)
>
> diff --git a/Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c
> b/Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c
> new file mode 100644
> index ..07958b1e392d
> --- /dev/null
> +++ b/Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c
> @@ -0,0 +1,1876 @@
> +/** @file
> +*
> +* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include
> +#include
> +#include "iMX6ClkPwr_private.h"
> +
> +static IMX_CLOCK_TREE_CACHE mImxpClockPwrCache; // Cached clock value
STATIC
> +
> +STATIC CONST IMX_CCGR_INDEX ImxpCcgrIndexMap[] = {
Add m-prefix.
> + {0, 0}, // MX6_AIPS_TZ1_CLK_ENABLE
> + {0, 1}, // MX6_AIPS_TZ2_CLK_ENABLE
> + {0, 2}, // MX6_APBHDMA_HCLK_ENABLE
> + {0, 3}, // MX6_ASRC_CLK_ENABLE
> + {0, 4}, // MX6_CAAM_SECURE_MEM_CLK_ENABLE
> + {0, 5}, // MX6_CAAM_WRAPPER_ACLK_ENABLE
> + {0, 6}, // MX6_CAAM_WRAPPER_IPG_ENABLE
> + {0, 7}, // MX6_CAN1_CLK_ENABLE
> + {0, 8}, // MX6_CAN1_SERIAL_CLK_ENABLE
> + {0, 9}, // MX6_CAN2_CLK_ENABLE
> + {0, 10}, // MX6_CAN2_SERIAL_CLK_ENABLE
> + {0, 11}, // MX6_ARM_DBG_CLK_ENABLE
> + {0, 12}, // MX6_DCIC1_CLK_ENABLE
> + {0, 13}, // MX6_DCIC2_CLK_ENABLE
> + {0, 14}, // MX6_DTCP_CLK_ENABLE
> + {1, 0}, // MX6_ECSPI1_CLK_ENABLE
> + {1, 1}, // MX6_ECSPI2_CLK_ENABLE
> + {1, 2}, // MX6_ECSPI3_CLK_ENABLE
> + {1, 3}, // MX6_ECSPI4_CLK_ENABLE
> + {1, 4}, // MX6_ECSPI5_CLK_ENABLE
> + {1, 5}, // MX6_ENET_CLK_ENABLE
> + {1, 6}, // MX6_EPIT1_CLK_ENABLE
> + {1, 7}, // MX6_EPIT2_CLK_ENABLE
> + {1, 8}, // MX6_ESAI_CLK_ENABLE
> + {1, 10}, // MX6_GPT_CLK_ENABLE
> + {1, 11}, // MX6_GPT_SERIAL_CLK_ENABLE
> + {1, 12}, // MX6_GPU2D_CLK_ENABLE
> + {1, 13}, // MX6_GPU3D_CLK_ENABLE
> + {2, 0}, // MX6_HDMI_TX_ENABLE
> + {2, 2}, // MX6_HDMI_TX_ISFRCLK_ENABLE
> + {2, 3}, // MX6_I2C1_SERIAL_CLK_ENABLE
> + {2, 4}, // MX6_I2C2_SERIAL_CLK_ENABLE
> + {2, 5}, // MX6_I2C3_SERIAL_CLK_ENABLE
> + {2, 6}, // MX6_IIM_CLK_ENABLE
> + {2, 7}, // MX6_IOMUX_IPT_CLK_IO_ENABLE
> + {2, 8}, // MX6_IPMUX1_CLK_ENABLE
> + {2, 9}, // MX6_IPMUX2_CLK_ENABLE
> + {2, 10}, // MX6_IPMUX3_CLK_ENABLE
> + {2, 11}, // MX6_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE
> + {2, 12}, // MX6_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE
> + {2, 13}, // MX6_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE
> + {3, 0}, // MX6_IPU1_IPU_CLK_ENABLE
> + {3, 1}, // MX6_IPU1_IPU_DI0_CLK_ENABLE
> + {3, 2}, // MX6_IPU1_IPU_DI1_CLK_ENABLE
> + {3, 3}, // MX6_IPU2_IPU_CLK_ENABLE
> + {3, 4}, // MX6_IPU2_IPU_DI0_CLK_ENABLE
> + {3, 5}, // MX6_IPU2_IPU_DI1_CLK_ENABLE
> + {3, 6}, // MX6_LDB_DI0_CLK_ENABLE
> + {3, 7}, // MX6_LDB_DI1_CLK_ENABLE
> + {3, 8}, // MX6_MIPI_CORE_CFG_CLK_ENABLE
> + {3, 9}, // MX6_MLB_CLK_ENABLE
> + {3, 10}, // MX6_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE
> + {3, 12}, // MX6_MMDC_CORE_IPG_CLK_P0_ENABLE
> + {3, 14}, // MX6_OCRAM_CLK_ENABLE
> + {3, 15}, // MX6_OPENVGAXICLK_CLK_ROOT_ENABLE
> + {4, 0}, // MX6_PCIE_ROOT_ENABLE
> + {4, 4}, // MX6_PL301_MX6QFAST1_S133CLK_ENABLE
> + {4, 6}, // MX6_PL301_MX6QPER1_BCHCLK_ENABLE
> + {4, 7}, // MX6_PL301_MX6QPER2_MAINCLK_ENABLE
> + {4, 8}, // MX6_PWM1_CLK_ENABLE
> + {4, 9}, // MX6_PWM2_CLK_ENABLE
> + {4, 10}, // MX6_PWM3_CLK_ENABLE
> + {4, 11}, // MX6_PWM4_CLK_ENABLE
> + {4, 12}, // MX6_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE
> + {4, 13}, // MX6_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE
> + {4, 14}, // MX6_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE
> + {4, 15}, // MX6_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE
> + {5, 0}, // MX6_ROM_CLK_ENABLE
> + {5, 2}, // MX6_SATA_CLK_ENABLE
> + {5, 3}, // MX6_SDMA_CLK_ENABLE
> + {5, 6}, // MX6_SPBA_CLK_ENABLE
> + {5, 7}, // MX6_SPDIF_CLK_ENABLE
> + {5, 9}, // MX6_SSI1_CLK_ENABLE
> + {5, 10}, // MX6_SSI2_CLK_ENABLE
> + {5, 11}, // MX6_SSI3_CLK_ENABLE
> + {5, 12}, //
[edk2] [PATCH edk2-platforms 18/27] Silicon/NXP: Add i.MX6 Clock Library
This adds support for managing clocks on NXP i.MX6 SoC. It will
manipulate the Clock Gating registers (CCGR).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co
Cc: Ard Biesheuvel
Cc: Leif Lindholm
Cc: Michael D Kinney
---
Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c | 1876
Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwrLib.inf| 46 +
Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr_private.h | 221 +++
3 files changed, 2143 insertions(+)
diff --git a/Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c
b/Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c
new file mode 100644
index ..07958b1e392d
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Library/iMX6ClkPwrLib/iMX6ClkPwr.c
@@ -0,0 +1,1876 @@
+/** @file
+*
+* Copyright (c) 2018 Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
License
+* which accompanies this distribution. The full text of the license may be
found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+*
+**/
+
+#include
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include "iMX6ClkPwr_private.h"
+
+static IMX_CLOCK_TREE_CACHE mImxpClockPwrCache; // Cached clock value
+
+STATIC CONST IMX_CCGR_INDEX ImxpCcgrIndexMap[] = {
+ {0, 0}, // MX6_AIPS_TZ1_CLK_ENABLE
+ {0, 1}, // MX6_AIPS_TZ2_CLK_ENABLE
+ {0, 2}, // MX6_APBHDMA_HCLK_ENABLE
+ {0, 3}, // MX6_ASRC_CLK_ENABLE
+ {0, 4}, // MX6_CAAM_SECURE_MEM_CLK_ENABLE
+ {0, 5}, // MX6_CAAM_WRAPPER_ACLK_ENABLE
+ {0, 6}, // MX6_CAAM_WRAPPER_IPG_ENABLE
+ {0, 7}, // MX6_CAN1_CLK_ENABLE
+ {0, 8}, // MX6_CAN1_SERIAL_CLK_ENABLE
+ {0, 9}, // MX6_CAN2_CLK_ENABLE
+ {0, 10}, // MX6_CAN2_SERIAL_CLK_ENABLE
+ {0, 11}, // MX6_ARM_DBG_CLK_ENABLE
+ {0, 12}, // MX6_DCIC1_CLK_ENABLE
+ {0, 13}, // MX6_DCIC2_CLK_ENABLE
+ {0, 14}, // MX6_DTCP_CLK_ENABLE
+ {1, 0}, // MX6_ECSPI1_CLK_ENABLE
+ {1, 1}, // MX6_ECSPI2_CLK_ENABLE
+ {1, 2}, // MX6_ECSPI3_CLK_ENABLE
+ {1, 3}, // MX6_ECSPI4_CLK_ENABLE
+ {1, 4}, // MX6_ECSPI5_CLK_ENABLE
+ {1, 5}, // MX6_ENET_CLK_ENABLE
+ {1, 6}, // MX6_EPIT1_CLK_ENABLE
+ {1, 7}, // MX6_EPIT2_CLK_ENABLE
+ {1, 8}, // MX6_ESAI_CLK_ENABLE
+ {1, 10}, // MX6_GPT_CLK_ENABLE
+ {1, 11}, // MX6_GPT_SERIAL_CLK_ENABLE
+ {1, 12}, // MX6_GPU2D_CLK_ENABLE
+ {1, 13}, // MX6_GPU3D_CLK_ENABLE
+ {2, 0}, // MX6_HDMI_TX_ENABLE
+ {2, 2}, // MX6_HDMI_TX_ISFRCLK_ENABLE
+ {2, 3}, // MX6_I2C1_SERIAL_CLK_ENABLE
+ {2, 4}, // MX6_I2C2_SERIAL_CLK_ENABLE
+ {2, 5}, // MX6_I2C3_SERIAL_CLK_ENABLE
+ {2, 6}, // MX6_IIM_CLK_ENABLE
+ {2, 7}, // MX6_IOMUX_IPT_CLK_IO_ENABLE
+ {2, 8}, // MX6_IPMUX1_CLK_ENABLE
+ {2, 9}, // MX6_IPMUX2_CLK_ENABLE
+ {2, 10}, // MX6_IPMUX3_CLK_ENABLE
+ {2, 11}, // MX6_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE
+ {2, 12}, // MX6_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE
+ {2, 13}, // MX6_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE
+ {3, 0}, // MX6_IPU1_IPU_CLK_ENABLE
+ {3, 1}, // MX6_IPU1_IPU_DI0_CLK_ENABLE
+ {3, 2}, // MX6_IPU1_IPU_DI1_CLK_ENABLE
+ {3, 3}, // MX6_IPU2_IPU_CLK_ENABLE
+ {3, 4}, // MX6_IPU2_IPU_DI0_CLK_ENABLE
+ {3, 5}, // MX6_IPU2_IPU_DI1_CLK_ENABLE
+ {3, 6}, // MX6_LDB_DI0_CLK_ENABLE
+ {3, 7}, // MX6_LDB_DI1_CLK_ENABLE
+ {3, 8}, // MX6_MIPI_CORE_CFG_CLK_ENABLE
+ {3, 9}, // MX6_MLB_CLK_ENABLE
+ {3, 10}, // MX6_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE
+ {3, 12}, // MX6_MMDC_CORE_IPG_CLK_P0_ENABLE
+ {3, 14}, // MX6_OCRAM_CLK_ENABLE
+ {3, 15}, // MX6_OPENVGAXICLK_CLK_ROOT_ENABLE
+ {4, 0}, // MX6_PCIE_ROOT_ENABLE
+ {4, 4}, // MX6_PL301_MX6QFAST1_S133CLK_ENABLE
+ {4, 6}, // MX6_PL301_MX6QPER1_BCHCLK_ENABLE
+ {4, 7}, // MX6_PL301_MX6QPER2_MAINCLK_ENABLE
+ {4, 8}, // MX6_PWM1_CLK_ENABLE
+ {4, 9}, // MX6_PWM2_CLK_ENABLE
+ {4, 10}, // MX6_PWM3_CLK_ENABLE
+ {4, 11}, // MX6_PWM4_CLK_ENABLE
+ {4, 12}, // MX6_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE
+ {4, 13}, // MX6_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE
+ {4, 14}, // MX6_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE
+ {4, 15}, // MX6_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE
+ {5, 0}, // MX6_ROM_CLK_ENABLE
+ {5, 2}, // MX6_SATA_CLK_ENABLE
+ {5, 3}, // MX6_SDMA_CLK_ENABLE
+ {5, 6}, // MX6_SPBA_CLK_ENABLE
+ {5, 7}, // MX6_SPDIF_CLK_ENABLE
+ {5, 9}, // MX6_SSI1_CLK_ENABLE
+ {5, 10}, // MX6_SSI2_CLK_ENABLE
+ {5, 11}, // MX6_SSI3_CLK_ENABLE
+ {5, 12}, // MX6_UART_CLK_ENABLE
+ {5, 13}, // MX6_UART_SERIAL_CLK_ENABLE
+ {6, 0}, // MX6_USBOH3_CLK_ENABLE
+ {6, 1}, // MX6_USDHC1_CLK_ENABLE
+ {6, 2}, // MX6_USDHC2_CLK_ENABLE
+ {6, 3}, // MX6_USDHC3_CLK_ENABLE
+ {6, 4}, // MX6_USDHC4_CLK_ENABLE
+ {6, 5}, // MX6_EIM_SLOW_CLK_ENABLE
+ {6, 6}, // MX6_VDOAXICLK_CLK_ENABLE
+ {6, 7}, //
