When running on 32-bit ARM, we cannot decode the MMIO64 region, and so we don't set the EFI_PCI_HOST_BRIDGE_MEM64_DECODE flag in this case. However, with that flag cleared, it is no longer permitted to include a definition for the placement of the MMIO64 region either, so remove those as well if MDE_CPU_ARM is set (which is the same condition under which EFI_PCI_HOST_BRIDGE_MEM64_DECODE is cleared)
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org> --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 7c096f0801dd..117cf6cfd81b 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -109,8 +109,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { { SYNQUACER_PCI_SEG0_MMIO32_MIN, SYNQUACER_PCI_SEG0_MMIO32_MAX, MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem +#ifndef MDE_CPU_ARM { SYNQUACER_PCI_SEG0_MMIO64_MIN, SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G +#else + { MAX_UINT64, 0x0 }, // MemAbove4G +#endif { MAX_UINT64, 0x0 }, // PMem { MAX_UINT64, 0x0 }, // PMemAbove4G (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] @@ -130,8 +134,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { { SYNQUACER_PCI_SEG1_MMIO32_MIN, SYNQUACER_PCI_SEG1_MMIO32_MAX, MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem +#ifndef MDE_CPU_ARM { SYNQUACER_PCI_SEG1_MMIO64_MIN, SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G +#else + { MAX_UINT64, 0x0 }, // MemAbove4G +#endif { MAX_UINT64, 0x0 }, // PMem { MAX_UINT64, 0x0 }, // PMemAbove4G (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] -- 2.17.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel