Re: [edk2] [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver
在 2018/6/28 18:54, Ard Biesheuvel 写道: > On 28 June 2018 at 04:26, Ming wrote: >> >> >> 在 2018/6/27 15:33, Ard Biesheuvel 写道: >>> On 27 June 2018 at 09:04, Ming Huang wrote: Fix the issue of onboard Nic not work kerenl with AMD GPU and NVME SSD in board. The GPU don't support 64 MSI, so need to allocate INTx, but the default interrupt number 255 is invalid, so Change all the PCI Device interrupt number to 0. >>> >>> Could you please try to explain in more detail what the problem is you >>> are solving, and why you think it should be solved in the firmware? >>> What does '64 MSI' mean? And where does the default of 255 come from? >>> >>> >> >> With AMD GPU and NVMe in board, the onboard Nic(hns-nic) can not work in >> ubuntu os. >> The AMD GPU has two devices: >> PCI device amdgpu 000d:33:00.0, snd_hda_intel 000d:33:00.1 >> The MSI is 64bit address in D05, and snd_hda_intel don't support 64bit MSI >> address, > > Legacy PCIe endpoints are permitted to only implement support for > 32-bit addressing of the MSI doorbell register, which is why it is > generally a good idea to put that below 4 GB in the physical address > space. > > So how is this implemented on D05? How are the PCIe host bridge > inbound windows configured? Any chance you could fix this by remapping > inbound transactions so the MSI doorbell appears at a 32-bit > addressable offset? > Inbound windows is not configured on D05. Maybe There are some risks if we configure inbound windows considering D05 has been running stably for a long time. Thanks. > >> so snd_hda_intel use the 255 irq. The onboard Nic register 255 irq failed. >> The 255 is the default value of PCI_INTERRUPT_LINE reg (0x3C). >> There is not a proper solution in kernel.This patch is a workaround in >> firmware. >> >> error log in kernel: >> Mar 1 00:27:07 ubuntu kernel: [ 25.581265] snd_hda_intel 000d:33:00.1: >> Device has broken 64-bit MSI but arch tried to assign one above 4Gl >> >> Mar 1 00:36:39 ubuntu kernel: [ 600.751276] genirq: Flags mismatch irq >> 255. 0001 (enahisic2i0-tx1) vs. 0081 (snd_hda_intel:card0) >> >> Mar 1 00:36:39 ubuntu kernel: [ 600.761137] hns-nic HISI00C2:00 >> enahisic2i0: request irq(255) fail >> >> Thanks. >> >>> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++ 4 files changed, 148 insertions(+) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d98a..0e6d5912a0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -629,6 +629,7 @@ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf # # Memory test diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 37d9cc0c18..32374e245e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c new file mode 100644 index 00..8519b7139d --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +VOID +SetIntLine (
Re: [edk2] [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver
On 28 June 2018 at 04:26, Ming wrote:
>
>
> 在 2018/6/27 15:33, Ard Biesheuvel 写道:
>> On 27 June 2018 at 09:04, Ming Huang wrote:
>>> Fix the issue of onboard Nic not work kerenl with AMD GPU and
>>> NVME SSD in board. The GPU don't support 64 MSI, so need to
>>> allocate INTx, but the default interrupt number 255 is invalid,
>>> so Change all the PCI Device interrupt number to 0.
>>>
>>
>> Could you please try to explain in more detail what the problem is you
>> are solving, and why you think it should be solved in the firmware?
>> What does '64 MSI' mean? And where does the default of 255 come from?
>>
>>
>
> With AMD GPU and NVMe in board, the onboard Nic(hns-nic) can not work in
> ubuntu os.
> The AMD GPU has two devices:
> PCI device amdgpu 000d:33:00.0, snd_hda_intel 000d:33:00.1
> The MSI is 64bit address in D05, and snd_hda_intel don't support 64bit MSI
> address,
Legacy PCIe endpoints are permitted to only implement support for
32-bit addressing of the MSI doorbell register, which is why it is
generally a good idea to put that below 4 GB in the physical address
space.
So how is this implemented on D05? How are the PCIe host bridge
inbound windows configured? Any chance you could fix this by remapping
inbound transactions so the MSI doorbell appears at a 32-bit
addressable offset?
> so snd_hda_intel use the 255 irq. The onboard Nic register 255 irq failed.
> The 255 is the default value of PCI_INTERRUPT_LINE reg (0x3C).
> There is not a proper solution in kernel.This patch is a workaround in
> firmware.
>
> error log in kernel:
> Mar 1 00:27:07 ubuntu kernel: [ 25.581265] snd_hda_intel 000d:33:00.1:
> Device has broken 64-bit MSI but arch tried to assign one above 4Gl
>
> Mar 1 00:36:39 ubuntu kernel: [ 600.751276] genirq: Flags mismatch irq 255.
> 0001 (enahisic2i0-tx1) vs. 0081 (snd_hda_intel:card0)
>
> Mar 1 00:36:39 ubuntu kernel: [ 600.761137] hns-nic HISI00C2:00
> enahisic2i0: request irq(255) fail
>
> Thanks.
>
>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Ming Huang
>>> Signed-off-by: Heyi Guo
>>> ---
>>> Platform/Hisilicon/D05/D05.dsc | 1 +
>>> Platform/Hisilicon/D05/D05.fdf | 1 +
>>> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99
>>>
>>> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47
>>> ++
>>> 4 files changed, 148 insertions(+)
>>>
>>> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
>>> index b6e1a9d98a..0e6d5912a0 100644
>>> --- a/Platform/Hisilicon/D05/D05.dsc
>>> +++ b/Platform/Hisilicon/D05/D05.dsc
>>> @@ -629,6 +629,7 @@
>>>
>>>
>>>
>>> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
>>> + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>>>
>>>#
>>># Memory test
>>> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
>>> index 37d9cc0c18..32374e245e 100644
>>> --- a/Platform/Hisilicon/D05/D05.fdf
>>> +++ b/Platform/Hisilicon/D05/D05.fdf
>>> @@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE
>>>INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
>>>INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
>>>INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
>>> + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>>>
>>>INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>>
>>> diff --git
>>> a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
>>> b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
>>> new file mode 100644
>>> index 00..8519b7139d
>>> --- /dev/null
>>> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
>>> @@ -0,0 +1,99 @@
>>> +/** @file
>>> +*
>>> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>>> +* Copyright (c) 2016, Linaro Limited. All rights reserved.
>>> +*
>>> +* This program and the accompanying materials
>>> +* are licensed and made available under the terms and conditions of the
>>> BSD License
>>> +* which accompanies this distribution. The full text of the license may
>>> be found at
>>> +* http://opensource.org/licenses/bsd-license.php
>>> +*
>>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
>>> IMPLIED.
>>> +*
>>> +**/
>>> +
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +#include
>>> +
>>> +VOID
>>> +SetIntLine (
>>> + )
>>> +{
>>> + EFI_STATUS Status;
>>> + UINTN HandleIndex;
>>> + EFI_HANDLE *HandleBuffer;
>>> + UINTN HandleCount;
>>> + EFI_PCI_IO_PROTOCOL*PciIo;
>>> + UINT8 INTLine;
>>> + UINTN
Re: [edk2] [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver
On 27 June 2018 at 09:04, Ming Huang wrote:
> Fix the issue of onboard Nic not work kerenl with AMD GPU and
> NVME SSD in board. The GPU don't support 64 MSI, so need to
> allocate INTx, but the default interrupt number 255 is invalid,
> so Change all the PCI Device interrupt number to 0.
>
Could you please try to explain in more detail what the problem is you
are solving, and why you think it should be solved in the firmware?
What does '64 MSI' mean? And where does the default of 255 come from?
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang
> Signed-off-by: Heyi Guo
> ---
> Platform/Hisilicon/D05/D05.dsc | 1 +
> Platform/Hisilicon/D05/D05.fdf | 1 +
> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99
>
> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47
> ++
> 4 files changed, 148 insertions(+)
>
> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
> index b6e1a9d98a..0e6d5912a0 100644
> --- a/Platform/Hisilicon/D05/D05.dsc
> +++ b/Platform/Hisilicon/D05/D05.dsc
> @@ -629,6 +629,7 @@
>
>
>
> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
> + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>
>#
># Memory test
> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
> index 37d9cc0c18..32374e245e 100644
> --- a/Platform/Hisilicon/D05/D05.fdf
> +++ b/Platform/Hisilicon/D05/D05.fdf
> @@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE
>INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
>INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
>INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
> + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>
>INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>
> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
> b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
> new file mode 100644
> index 00..8519b7139d
> --- /dev/null
> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
> @@ -0,0 +1,99 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2016, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD
> License
> +* which accompanies this distribution. The full text of the license may be
> found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> IMPLIED.
> +*
> +**/
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +VOID
> +SetIntLine (
> + )
> +{
> + EFI_STATUS Status;
> + UINTN HandleIndex;
> + EFI_HANDLE *HandleBuffer;
> + UINTN HandleCount;
> + EFI_PCI_IO_PROTOCOL*PciIo;
> + UINT8 INTLine;
> + UINTN Segment;
> + UINTN Bus;
> + UINTN Device;
> + UINTN Fun;
> +
> + Status = gBS->LocateHandleBuffer (
> + ByProtocol,
> + ,
> + NULL,
> + ,
> +
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n"));
> + gBS->FreePool ((VOID *)HandleBuffer);
> + return;
> + }
> +
> + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
> + Status = gBS->HandleProtocol (
> + HandleBuffer[HandleIndex],
> + ,
> + (VOID **)
> + );
> + if (EFI_ERROR (Status)) {
> + continue;
> + }
> +
> + INTLine = 0;
> + (VOID)PciIo->Pci.Write (
> + PciIo,
> + EfiPciIoWidthUint8,
> + PCI_INT_LINE_OFFSET,
> + 1,
> + );
> + (VOID)PciIo->GetLocation (PciIo, , , , );
> + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device,
> Fun));
> + }
> +
> + gBS->FreePool ((VOID *)HandleBuffer);
> + return;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformMiscDxeEntry (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT Event;
> +
> + Status = gBS->CreateEventEx (
> + EVT_NOTIFY_SIGNAL,
> + TPL_CALLBACK,
> +
[edk2] [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver
Fix the issue of onboard Nic not work kerenl with AMD GPU and
NVME SSD in board. The GPU don't support 64 MSI, so need to
allocate INTx, but the default interrupt number 255 is invalid,
so Change all the PCI Device interrupt number to 0.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
Signed-off-by: Heyi Guo
---
Platform/Hisilicon/D05/D05.dsc | 1 +
Platform/Hisilicon/D05/D05.fdf | 1 +
Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99
Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47
++
4 files changed, 148 insertions(+)
diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index b6e1a9d98a..0e6d5912a0 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -629,6 +629,7 @@
Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+ Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
#
# Memory test
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 37d9cc0c18..32374e245e 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+ INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
new file mode 100644
index 00..8519b7139d
--- /dev/null
+++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
@@ -0,0 +1,99 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
License
+* which accompanies this distribution. The full text of the license may be
found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
IMPLIED.
+*
+**/
+
+#include
+#include
+#include
+#include
+#include
+
+VOID
+SetIntLine (
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleIndex;
+ EFI_HANDLE *HandleBuffer;
+ UINTN HandleCount;
+ EFI_PCI_IO_PROTOCOL*PciIo;
+ UINT8 INTLine;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Fun;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ ,
+ NULL,
+ ,
+
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n"));
+ gBS->FreePool ((VOID *)HandleBuffer);
+ return;
+ }
+
+ for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+ Status = gBS->HandleProtocol (
+ HandleBuffer[HandleIndex],
+ ,
+ (VOID **)
+ );
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+
+ INTLine = 0;
+ (VOID)PciIo->Pci.Write (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_INT_LINE_OFFSET,
+ 1,
+ );
+ (VOID)PciIo->GetLocation (PciIo, , , , );
+ DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device,
Fun));
+ }
+
+ gBS->FreePool ((VOID *)HandleBuffer);
+ return;
+}
+
+EFI_STATUS
+EFIAPI
+PlatformMiscDxeEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_EVENT Event;
+
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ SetIntLine,
+ NULL,
+ ,
+
+ );
+ if (EFI_ERROR (Status)) {
+DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status));
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
new file mode 100644
index 00..0b365e7a53
--- /dev/null
+++
