This patch is to unify D0x. Add pGBL_INTERFACE struct define
and remove useless interfece. Replace DMRC pGblData with pGblInterface;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang
---
Silicon/Hisilicon/Include/Library/HwMemInitLib.h| 356
Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 4 +-
Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c | 26 +-
3 files changed, 78 insertions(+), 308 deletions(-)
diff --git a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
index 2663cad836..e1310e854c 100644
--- a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
+++ b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
@@ -50,48 +50,6 @@ typedef enum {
DDR_FREQ_MAX
} DDR_FREQUENCY_INDEX;
-typedef struct _DDR_FREQ_TCK
-{
-UINT32 ddrFreq;
-UINT32 ddrCk;
-}DDR_FREQ_TCK;
-
-typedef struct _GBL_CFG{
-
-
-}GBL_CFG;
-
-typedef struct _GBL_VAR{
-
-
-}GBL_VAR;
-
-typedef struct _GBL_NVDATA{
-
-
-}GBL_NVDATA;
-
-typedef struct _GOBAL {
-const GBL_CFG Config; // constant input data
-GBL_VAR Variable;// variable, volatile data
-GBL_NVDATANvData; // variable, non-volatile data for S3, warm boot
path
-UINT32PreBootFailed;
-}GOBAL, *PGOBAL;
-
-struct DDR_RANK {
-BOOLEAN Status;
-UINT16 RttNom;
-UINT16 RttPark;
-UINT16 RttWr;
-UINT16 MR0;
-UINT16 MR1;
-UINT16 MR2;
-UINT16 MR3;
-UINT16 MR4;
-UINT16 MR5;
-UINT16 MR6[9];
-};
-
struct baseMargin {
INT16 n;
INT16 p;
@@ -101,171 +59,7 @@ struct rankMargin {
struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
};
-typedef struct _DDR_DIMM{
-BOOLEAN Status;
-UINT8 mapout;
-UINT8 DramType; //Byte 2
-UINT8 ModuleType; //Byte 3
-UINT8 ExtendModuleType;
-UINT8 SDRAMCapacity; //Byte 4
-UINT8 BankNum;
-UINT8 BGNum; //Byte 4 For DDR4
-UINT8 RowBits;//Byte 5
-UINT8 ColBits;//Byte 5
-UINT8 SpdVdd; //Byte 6
-UINT8 DramWidth; //Byte 7
-UINT8 RankNum;//Byte 7
-UINT8 PrimaryBusWidth;//Byte 8
-UINT8 ExtensionBusWidth; //Byte 8
-UINT32 Mtb;
-UINT32 Ftb;
-UINT32 minTck;
-UINT8 MtbDividend;
-UINT8 MtbDivsor;
-UINT8 nCL;
-UINT32 nRCD;
-UINT32 nRP;
-UINT8 SPDftb;
-UINT8 SpdMinTCK;
-UINT8 SpdMinTCKFtb;
-UINT8 SpdMaxTCK;
-UINT8 SpdMinTCL;
-UINT8 SpdMinTCLFtb;
-UINT8 SpdMinTWR;
-UINT8 SpdMinTRCD;
-UINT8 SpdMinTRCDFtb;
-UINT8 SpdMinTRRD;
-UINT8 SpdMinTRRDL;
-UINT16 SpdMinTRAS;
-UINT16 SpdMinTRC;
-UINT16 SpdMinTRCFtb;
-UINT16 SpdMinTRFC;
-UINT8 SpdMinTWTR;
-UINT8 SpdMinTRTP;
-UINT8 SpdMinTAA;
-UINT8 SpdMinTAAFtb;
-UINT8 SpdMinTFAW;
-UINT8 SpdMinTRP;
-UINT8 SpdMinTRPFtb;
-UINT8 SpdMinTCCDL;
-UINT8 SpdMinTCCDLFtb;
-UINT8 SpdAddrMap;
-UINT8 SpdModuleAttr;
-
-UINT8 SpdModPart[SPD_MODULE_PART]; // Module Part Number
-UINT8 SpdModPartDDR4[SPD_MODULE_PART_DDR4]; // Module Part
Number DDR4
-UINT16 SpdMMfgId; // Module Mfg Id from SPD
-UINT16 SpdRMId; // Register Manufacturer Id
-UINT16 SpdMMDate; // Module Manufacturing Date
-UINT32 SpdSerialNum;
-UINT16 DimmSize;
-UINT16 DimmSpeed;
-UINT32 RankSize;
-UINT8 SpdMirror; //Denote the dram address mapping is standard mode
or mirrored mode
-struct DDR_RANK Rank[MAX_RANK_DIMM];
-}DDR_DIMM;
-
-typedef struct {
-UINT32 ddrcTiming0;
-UINT32 ddrcTiming1;
-UINT32 ddrcTiming2;
-UINT32 ddrcTiming3;
-UINT32 ddrcTiming4;
-UINT32 ddrcTiming5;
-UINT32 ddrcTiming6;
-UINT32 ddrcTiming7;
-UINT32 ddrcTiming8;
-}DDRC_TIMING;
-
-typedef struct _MARGIN_RESULT{
-UINT32 OptimalDramVref[12];
-UINT32 optimalPhyVref[18];
-}MARGIN_RESULT;
-
-typedef struct _DDR_Channel{
-BOOLEAN Status;
-UINT8 CurrentDimmNum;
-UINT8 CurrentRankNum;
-UINT16 RankPresent;
-UINT8 DramType;
-UINT8 DramWidth;
-UINT8 ModuleType;
-UINT32 MemSize;
-UINT32 tck;
-UINT32 ratio;
-UINT32 CLSupport;
-UINT32 minTck;
-UINT32 taref;
-UINT32 nAA;
-UINT32 nAOND;
-UINT32 nCKE;
-UINT32 nCL;
-UINT32 nCCDL;
-UINT32 nCKSRX;
-
