Re: [edk2] [PATCH v3] ArmPlatformPkg/ArmJunoPkg: Add the correct SPI interrupt numbers for the MSI range
Thanks guys, Committed as SVN r18723 (with one trailing space and one spurious line break deleted in Madt.aslc, and subject/message trimmed down to 72 chars). Regards, Leif On 3 November 2015 at 10:41, Ryan Harkin wrote: > Thanks Jeremy. > > On 2 November 2015 at 20:54, Jeremy Linton wrote: >> The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware >> that has some memory mapped locations that can trigger traditional SPI >> interrupts. This allows some basic PCIe MSI capabilities. >> >> Setup the SPI range that is mapped by the MSI window. This range is described >> in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is described as >> "GICv2m PCI Express MSI". In the future when these tables are generated >> programmatically the information may be found in the MSI_TYPER register as >> well. >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Jeremy Linton > Reviewed-by: Ryan Harkin > >> --- >> ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc | 4 +++- >> ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h | 5 + >> 2 files changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc >> b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc >> index d63a19b..f7e4e52 100644 >> --- a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc >> +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc >> @@ -117,9 +117,11 @@ >>EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1 >>1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, >> FixedPcdGet32 (PcdGicInterruptInterfaceBase), >>0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), >> + >> }, >> EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 >> (PcdGicDistributorBase), 0), >> -EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, 0, 0) >> +// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, >> PhysicalBaseAddress, Flags, SPICount, SPIBase) >> +EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, >> ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) >>}; >> #endif >> >> diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h >> b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h >> index 9928c5a..d01d136 100644 >> --- a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h >> +++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h >> @@ -40,9 +40,14 @@ >> #define ARM_JUNO_PERIPHERALS_BASE 0x2000 >> #define ARM_JUNO_PERIPHERALS_SZ 0x0E00 >> >> +// PCIe MSI address window >> #define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c >> #define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB >> >> +// PCIe MSI to SPI mapping range >> +#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224 >> +#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is >> 351, 351-224=127 >> + >> // On-Chip non-secure SRAM >> #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E00 >> #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB >> -- >> 2.4.3 >> >> ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
Re: [edk2] [PATCH v3] ArmPlatformPkg/ArmJunoPkg: Add the correct SPI interrupt numbers for the MSI range
Thanks Jeremy. On 2 November 2015 at 20:54, Jeremy Linton wrote: > The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware > that has some memory mapped locations that can trigger traditional SPI > interrupts. This allows some basic PCIe MSI capabilities. > > Setup the SPI range that is mapped by the MSI window. This range is described > in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is described as > "GICv2m PCI Express MSI". In the future when these tables are generated > programmatically the information may be found in the MSI_TYPER register as > well. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jeremy Linton Reviewed-by: Ryan Harkin > --- > ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc | 4 +++- > ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h | 5 + > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc > b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc > index d63a19b..f7e4e52 100644 > --- a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc > +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc > @@ -117,9 +117,11 @@ >EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1 >1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 > (PcdGicInterruptInterfaceBase), >0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), > + > }, > EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 > (PcdGicDistributorBase), 0), > -EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, 0, 0) > +// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, > PhysicalBaseAddress, Flags, SPICount, SPIBase) > +EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, > ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) >}; > #endif > > diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h > b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h > index 9928c5a..d01d136 100644 > --- a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h > +++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h > @@ -40,9 +40,14 @@ > #define ARM_JUNO_PERIPHERALS_BASE 0x2000 > #define ARM_JUNO_PERIPHERALS_SZ 0x0E00 > > +// PCIe MSI address window > #define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c > #define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB > > +// PCIe MSI to SPI mapping range > +#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224 > +#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is > 351, 351-224=127 > + > // On-Chip non-secure SRAM > #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E00 > #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB > -- > 2.4.3 > > ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
[edk2] [PATCH v3] ArmPlatformPkg/ArmJunoPkg: Add the correct SPI interrupt numbers for the MSI range
The JunoR1 has a GICv2m which is a GICv2 with a little piece of hardware that has some memory mapped locations that can trigger traditional SPI interrupts. This allows some basic PCIe MSI capabilities. Setup the SPI range that is mapped by the MSI window. This range is described in the JunoR1 SoC TRM, table 3-3. Under Interrupt ID 244-351 is described as "GICv2m PCI Express MSI". In the future when these tables are generated programmatically the information may be found in the MSI_TYPER register as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton --- ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc | 4 +++- ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h | 5 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc index d63a19b..f7e4e52 100644 --- a/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc +++ b/ArmPlatformPkg/ArmJunoPkg/AcpiTables/Madt.aslc @@ -117,9 +117,11 @@ EFI_ACPI_5_1_GICC_STRUCTURE_INIT( // A57-1 1, 5, GET_MPID(0, 1), EFI_ACPI_5_0_GIC_ENABLED, 38, FixedPcdGet32 (PcdGicInterruptInterfaceBase), 0x2C06F000, 0x2C04F000, 25, 0 /* GicRBase */), + }, EFI_ACPI_5_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorBase), 0), -EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, 0, 0) +// Format: EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(GicMsiFrameId, PhysicalBaseAddress, Flags, SPICount, SPIBase) +EFI_ACPI_6_0_GIC_MSI_FRAME_INIT(0, ARM_JUNO_GIV2M_MSI_BASE, 0, ARM_JUNO_GIV2M_MSI_SPI_COUNT, ARM_JUNO_GIV2M_MSI_SPI_BASE) }; #endif diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h index 9928c5a..d01d136 100644 --- a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h +++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h @@ -40,9 +40,14 @@ #define ARM_JUNO_PERIPHERALS_BASE 0x2000 #define ARM_JUNO_PERIPHERALS_SZ 0x0E00 +// PCIe MSI address window #define ARM_JUNO_GIV2M_MSI_BASE 0x2c1c #define ARM_JUNO_GIV2M_MSI_SZ SIZE_256KB +// PCIe MSI to SPI mapping range +#define ARM_JUNO_GIV2M_MSI_SPI_BASE 224 +#define ARM_JUNO_GIV2M_MSI_SPI_COUNT 127 //TRM says last SPI is 351, 351-224=127 + // On-Chip non-secure SRAM #define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E00 #define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB -- 2.4.3 ___ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
