Marvell firmware allows to use SiP services other than for ComPhy handling. In order to avoid spreading the SMC ID's definitions across many files, introduce common header for that purpose.
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <m...@semihalf.com> --- Silicon/Marvell/Include/IndustryStandard/MvSmc.h | 23 ++++++++++++++++++++ Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 8 +++---- Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 14 ++++++------ 3 files changed, 33 insertions(+), 12 deletions(-) create mode 100644 Silicon/Marvell/Include/IndustryStandard/MvSmc.h diff --git a/Silicon/Marvell/Include/IndustryStandard/MvSmc.h b/Silicon/Marvell/Include/IndustryStandard/MvSmc.h new file mode 100644 index 0000000..2d1542a --- /dev/null +++ b/Silicon/Marvell/Include/IndustryStandard/MvSmc.h @@ -0,0 +1,23 @@ +/** +* +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __MV_SMC_H__ +#define __MV_SMC_H__ + +/* Marvell SiP services SMC ID's */ +#define MV_SMC_ID_COMPHY_POWER_ON 0x82000001 +#define MV_SMC_ID_COMPHY_POWER_OFF 0x82000002 +#define MV_SMC_ID_COMPHY_PLL_LOCK 0x82000003 + +#endif //__MV_SMC_H__ diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h index d156af6..9fd6602 100644 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h @@ -35,16 +35,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef __COMPHY_SIP_SVC_H__ #define __COMPHY_SIP_SVC_H__ +#include <IndustryStandard/MvSmc.h> + /* * All values in this file are defined externally and used * for the SerDes configuration via SiP services. */ -/* Firmware related definitions used for SMC calls */ -#define MV_SIP_COMPHY_POWER_ON 0x82000001 -#define MV_SIP_COMPHY_POWER_OFF 0x82000002 -#define MV_SIP_COMPHY_PLL_LOCK 0x82000003 - +/* Helper macros for passing ComPhy parameters to the EL3 */ #define COMPHY_FW_MODE_FORMAT(mode) (mode << 12) #define COMPHY_FW_FORMAT(mode, idx, speeds) \ ((mode << 12) | (idx << 8) | (speeds << 2)) diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c index 2abb006..4f85676 100755 --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c @@ -163,7 +163,7 @@ ComPhySataPowerUp ( ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); - Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, ComPhyBase, Lane, COMPHY_FW_FORMAT (COMPHY_SATA_MODE, @@ -175,7 +175,7 @@ ComPhySataPowerUp ( ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); - Status = ComPhySmc (MV_SIP_COMPHY_PLL_LOCK, + Status = ComPhySmc (MV_SMC_ID_COMPHY_PLL_LOCK, ComPhyBase, Lane, COMPHY_FW_FORMAT (COMPHY_SATA_MODE, @@ -234,7 +234,7 @@ ComPhyCp110Init ( case COMPHY_TYPE_PCIE1: case COMPHY_TYPE_PCIE2: case COMPHY_TYPE_PCIE3: - Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, PtrChipCfg->ComPhyBaseAddr, Lane, COMPHY_FW_PCIE_FORMAT (PcieWidth, @@ -269,7 +269,7 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_USB3_HOST0: case COMPHY_TYPE_USB3_HOST1: - Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, PtrChipCfg->ComPhyBaseAddr, Lane, COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE)); @@ -278,7 +278,7 @@ ComPhyCp110Init ( case COMPHY_TYPE_SGMII1: case COMPHY_TYPE_SGMII2: case COMPHY_TYPE_SGMII3: - Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, PtrChipCfg->ComPhyBaseAddr, Lane, COMPHY_FW_FORMAT (COMPHY_SGMII_MODE, @@ -286,7 +286,7 @@ ComPhyCp110Init ( PtrComPhyMap->Speed)); break; case COMPHY_TYPE_SFI: - Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, PtrChipCfg->ComPhyBaseAddr, Lane, COMPHY_FW_FORMAT (COMPHY_SFI_MODE, @@ -295,7 +295,7 @@ ComPhyCp110Init ( break; case COMPHY_TYPE_RXAUI0: case COMPHY_TYPE_RXAUI1: - Status = ComPhySmc (MV_SIP_COMPHY_POWER_ON, + Status = ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, PtrChipCfg->ComPhyBaseAddr, Lane, COMPHY_FW_MODE_FORMAT (COMPHY_RXAUI_MODE)); -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
