Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

2015-11-27 Thread Paolo Bonzini 


On 27/11/2015 02:14, Yao, Jiewen wrote:
> [Jiewen] Do you mean KVM reject SMM write BIT16 of CR0 ? It is odd,
> because my patch sets W+P bit page table entries.

That's odd indeed.  All common OSes run with CR0.WP=1.  I'll try to
reproduce...

Paolo
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Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

2015-11-26 Thread Laszlo Ersek 
On 11/25/15 22:56, Yao, Jiewen wrote:
> Hi Mike
> Thanks for the suggestion.
> Previously, I just want to *ADD* without touch old logic. I will use your way 
> to do it.
> 
> -Original Message-
> From: Kinney, Michael D 
> Sent: Thursday, November 26, 2015 2:01 AM
> To: Yao, Jiewen; edk2-de...@ml01.01.org; Kinney, Michael D
> Cc: Fan, Jeff
> Subject: RE: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
> 
> Jiewen,
> 
> For IA32 assembly, can we combine into a single OR instruction that sets both 
> page enable and WP?
> For X64, does it make sense to use single OR instruction instead of 2 BTS 
> instructions as well?
> 
> With those updates,
> 
> Reviewed-by: Michael Kinney 
> 
> Thanks,
> 
> Mike
> 
>> -Original Message-
>> From: Yao, Jiewen
>> Sent: Wednesday, November 25, 2015 4:35 AM
>> To: edk2-de...@ml01.01.org
>> Cc: Yao, Jiewen ; Fan, Jeff ; 
>> Kinney, Michael D 
>> Subject: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
>>
>> So that we can use write-protection for code later.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: "Yao, Jiewen" 
>> Cc: "Fan, Jeff" 
>> Cc: "Kinney, Michael D" 
>> ---
>>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 1 +
>>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 1 +
>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S| 1 +
>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm  | 1 +
>>  4 files changed, 4 insertions(+)
>>
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>> index 7e1787c..8e64ce8 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>> @@ -142,6 +142,7 @@ L13:
>>
>>  movl%cr0, %ebx
>>  orl $0x08000, %ebx # enable paging
>> +orl $0x1, %ebx # set WP
>>  movl%ebx, %cr0
>>  lealDSC_OFFSET(%edi),%ebx
>>  movwDSC_DS(%ebx),%ax
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>> index e6af344..a955785 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>> @@ -148,6 +148,7 @@ gSmiCr3 DD  ?
>>
>>  mov ebx, cr0
>>  or  ebx, 08000h ; enable paging
>> +or  ebx, 1h ; set WP
>>  mov cr0, ebx
>>  lea ebx, [edi + DSC_OFFSET]
>>  mov ax, [ebx + DSC_DS]
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>> index 1d40819..8050a00 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>> @@ -163,6 +163,7 @@ NxeDone:
>>  wrmsr
>>  movq%cr0, %rbx
>>  btsl$31, %ebx
>> +btsl$16, %ebx   # set WP
>>  movq%rbx, %cr0
>>  retf
>>  LongMode:   # long mode (64-bit code) starts 
>> here
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>> index 6e1d3f1..db170d6 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>> @@ -159,6 +159,7 @@ Base:
>>  wrmsr
>>  mov rbx, cr0
>>  bts ebx, 31
>> +bts ebx, 16; set WP
>>  mov cr0, rbx
>>  retf
>>  @LongMode:  ; long mode (64-bit code) starts 
>> here
>> --
>> 1.9.5.msysgit.0

This patch (= SVN r18960) breaks the 32-bit (Ia32) build of the OVMF SMM series.

KVM "rejects" the guest soon after the SMBASE relocation.

These are the last messages from the OVMF debug log:

> Loading SMM driver at 0x0007FFD2000 EntryPoint=0x0007FFD2253 
> PiSmmCpuDxeSmm.efi
> SMRR Base: 0x7F80, SMRR Size: 0x80
> PcdCpuSmmCodeAccessCheckEnable = 1
> SMRAM TileSize = 0x2000 (0x1000, 0x1000)
> SMRAM SaveState Buffer (0x7FFC4000, 0xE000)
> CPU[000]  APIC ID=  SMBASE=7FFBC000  SaveState=7FFCBC00  Size=0400
> CPU[001]  APIC ID=0002  SMBASE=7FFBE000  SaveState=7FFCDC00  Size=0400
> CPU[002]  APIC ID=0003  SMBASE=7FFC  SaveState=7FFCFC00  Size=0400
> CPU[003]  APIC ID=0001  SMBASE=7FFC2000  SaveState=7FFD1C00  Size=0400
> InstallProtocolInterface: 26EEB3DE-B689-492E-80F0-BE8BD7DA4BA7 7FFE0FD0
> SMM IPL registered SMM Entry Point address 7FFF19AE
> SmmInstallProtocolInterface: EB346B97-975F-4A9F-8B22-F8E92BB3D569 7FFE0F68
> SmmInstallProtocolInterface: 1D202CAB-C8AB-4D5C-94F7-3CFCC0D3D335 7FFE0FDC
> SMM S3 SMRAM Structure = 7F5816C0
> SMM S3 Structure = 7F80
> SMM CPU Module exit from SMRAM with EFI_SUCCESS
> SMM IPL closed SMRAM window

QEMU logs the following:

> KVM: entry failed, hardware error 0x8021
> 
> If

Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

2015-11-26 Thread Yao, Jiewen 
Hi Laszlo
Comments below:

-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Laszlo 
Ersek
Sent: Friday, November 27, 2015 5:57 AM
To: Yao, Jiewen; Kinney, Michael D; edk2-de...@ml01.01.org
Cc: Paolo Bonzini; Fan, Jeff
Subject: Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

On 11/25/15 22:56, Yao, Jiewen wrote:
> Hi Mike
> Thanks for the suggestion.
> Previously, I just want to *ADD* without touch old logic. I will use your way 
> to do it.
> 
> -Original Message-
> From: Kinney, Michael D
> Sent: Thursday, November 26, 2015 2:01 AM
> To: Yao, Jiewen; edk2-de...@ml01.01.org; Kinney, Michael D
> Cc: Fan, Jeff
> Subject: RE: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
> 
> Jiewen,
> 
> For IA32 assembly, can we combine into a single OR instruction that sets both 
> page enable and WP?
> For X64, does it make sense to use single OR instruction instead of 2 BTS 
> instructions as well?
> 
> With those updates,
> 
> Reviewed-by: Michael Kinney <michael.d.kin...@intel.com>
> 
> Thanks,
> 
> Mike
> 
>> -Original Message-
>> From: Yao, Jiewen
>> Sent: Wednesday, November 25, 2015 4:35 AM
>> To: edk2-de...@ml01.01.org
>> Cc: Yao, Jiewen <jiewen@intel.com>; Fan, Jeff 
>> <jeff@intel.com>; Kinney, Michael D <michael.d.kin...@intel.com>
>> Subject: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
>>
>> So that we can use write-protection for code later.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: "Yao, Jiewen" <jiewen@intel.com>
>> Cc: "Fan, Jeff" <jeff@intel.com>
>> Cc: "Kinney, Michael D" <michael.d.kin...@intel.com>
>> ---
>>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 1 +
>>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 1 +
>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S| 1 +
>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm  | 1 +
>>  4 files changed, 4 insertions(+)
>>
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>> index 7e1787c..8e64ce8 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>> @@ -142,6 +142,7 @@ L13:
>>
>>  movl%cr0, %ebx
>>  orl $0x08000, %ebx # enable paging
>> +orl $0x1, %ebx # set WP
>>  movl%ebx, %cr0
>>  lealDSC_OFFSET(%edi),%ebx
>>  movwDSC_DS(%ebx),%ax
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>> index e6af344..a955785 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>> @@ -148,6 +148,7 @@ gSmiCr3 DD  ?
>>
>>  mov ebx, cr0
>>  or  ebx, 08000h ; enable paging
>> +or  ebx, 1h ; set WP
>>  mov cr0, ebx
>>  lea ebx, [edi + DSC_OFFSET]
>>  mov ax, [ebx + DSC_DS]
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>> index 1d40819..8050a00 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>> @@ -163,6 +163,7 @@ NxeDone:
>>  wrmsr
>>  movq%cr0, %rbx
>>  btsl$31, %ebx
>> +btsl$16, %ebx   # set WP
>>  movq%rbx, %cr0
>>  retf
>>  LongMode:   # long mode (64-bit code) starts 
>> here
>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm 
>> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>> index 6e1d3f1..db170d6 100644
>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>> @@ -159,6 +159,7 @@ Base:
>>  wrmsr
>>  mov rbx, cr0
>>  bts ebx, 31
>> +bts ebx, 16; set WP
>>  mov cr0, rbx
>>  retf
>>  @LongMode:  ; long mode (64-bit code) starts 
>> here
>> --
>> 1.9.5.msysgit.0

This patch (= SVN r18960) breaks the 32-bit (Ia32) build of the OVMF SMM series.

KVM "rejects" the guest soon after the SMBASE relocation.

These are the last messages from the OVMF debug log:

> Loading SMM driver at 0x0007FFD2000 EntryPoint=0x0007FFD2253 
> PiSmmCpuDxeSmm.efi SMRR Base: 0x7F80, SMRR

Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

2015-11-26 Thread Laszlo Ersek 
On 11/27/15 02:14, Yao, Jiewen wrote:
> Hi Laszlo
> Comments below:
> 
> -Original Message-
> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Laszlo 
> Ersek
> Sent: Friday, November 27, 2015 5:57 AM
> To: Yao, Jiewen; Kinney, Michael D; edk2-de...@ml01.01.org
> Cc: Paolo Bonzini; Fan, Jeff
> Subject: Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
> 
> On 11/25/15 22:56, Yao, Jiewen wrote:
>> Hi Mike
>> Thanks for the suggestion.
>> Previously, I just want to *ADD* without touch old logic. I will use your 
>> way to do it.
>>
>> -Original Message-
>> From: Kinney, Michael D
>> Sent: Thursday, November 26, 2015 2:01 AM
>> To: Yao, Jiewen; edk2-de...@ml01.01.org; Kinney, Michael D
>> Cc: Fan, Jeff
>> Subject: RE: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
>>
>> Jiewen,
>>
>> For IA32 assembly, can we combine into a single OR instruction that sets 
>> both page enable and WP?
>> For X64, does it make sense to use single OR instruction instead of 2 BTS 
>> instructions as well?
>>
>> With those updates,
>>
>> Reviewed-by: Michael Kinney <michael.d.kin...@intel.com>
>>
>> Thanks,
>>
>> Mike
>>
>>> -Original Message-
>>> From: Yao, Jiewen
>>> Sent: Wednesday, November 25, 2015 4:35 AM
>>> To: edk2-de...@ml01.01.org
>>> Cc: Yao, Jiewen <jiewen@intel.com>; Fan, Jeff 
>>> <jeff@intel.com>; Kinney, Michael D <michael.d.kin...@intel.com>
>>> Subject: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
>>>
>>> So that we can use write-protection for code later.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.0
>>> Signed-off-by: "Yao, Jiewen" <jiewen@intel.com>
>>> Cc: "Fan, Jeff" <jeff@intel.com>
>>> Cc: "Kinney, Michael D" <michael.d.kin...@intel.com>
>>> ---
>>>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 1 +
>>>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 1 +
>>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S| 1 +
>>>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm  | 1 +
>>>  4 files changed, 4 insertions(+)
>>>
>>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S 
>>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>>> index 7e1787c..8e64ce8 100644
>>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
>>> @@ -142,6 +142,7 @@ L13:
>>>
>>>  movl%cr0, %ebx
>>>  orl $0x08000, %ebx # enable paging
>>> +orl $0x1, %ebx # set WP
>>>  movl%ebx, %cr0
>>>  lealDSC_OFFSET(%edi),%ebx
>>>  movwDSC_DS(%ebx),%ax
>>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm 
>>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>>> index e6af344..a955785 100644
>>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
>>> @@ -148,6 +148,7 @@ gSmiCr3 DD  ?
>>>
>>>  mov ebx, cr0
>>>  or  ebx, 08000h ; enable paging
>>> +or  ebx, 1h ; set WP
>>>  mov cr0, ebx
>>>  lea ebx, [edi + DSC_OFFSET]
>>>  mov ax, [ebx + DSC_DS]
>>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S 
>>> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>>> index 1d40819..8050a00 100644
>>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
>>> @@ -163,6 +163,7 @@ NxeDone:
>>>  wrmsr
>>>  movq%cr0, %rbx
>>>  btsl$31, %ebx
>>> +btsl$16, %ebx   # set WP
>>>  movq%rbx, %cr0
>>>  retf
>>>  LongMode:   # long mode (64-bit code) starts 
>>> here
>>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm 
>>> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>>> index 6e1d3f1..db170d6 100644
>>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
>>> @@ -159,6 +159,7 @@ Base:
>>>  wrmsr
>>>  mov rbx, cr0
>>>  bts ebx, 31
>>> +bts ebx, 16; set WP
>>>  mov cr

Re: [edk2] [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

2015-11-25 Thread Yao, Jiewen 
Hi Mike
Thanks for the suggestion.
Previously, I just want to *ADD* without touch old logic. I will use your way 
to do it.

-Original Message-
From: Kinney, Michael D 
Sent: Thursday, November 26, 2015 2:01 AM
To: Yao, Jiewen; edk2-de...@ml01.01.org; Kinney, Michael D
Cc: Fan, Jeff
Subject: RE: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.

Jiewen,

For IA32 assembly, can we combine into a single OR instruction that sets both 
page enable and WP?
For X64, does it make sense to use single OR instruction instead of 2 BTS 
instructions as well?

With those updates,

Reviewed-by: Michael Kinney 

Thanks,

Mike

> -Original Message-
> From: Yao, Jiewen
> Sent: Wednesday, November 25, 2015 4:35 AM
> To: edk2-de...@ml01.01.org
> Cc: Yao, Jiewen ; Fan, Jeff ; 
> Kinney, Michael D 
> Subject: [patch 2/2] UefiCpuPkg/PiSmmCpu: Always set WP in CR0.
> 
> So that we can use write-protection for code later.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: "Yao, Jiewen" 
> Cc: "Fan, Jeff" 
> Cc: "Kinney, Michael D" 
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S   | 1 +
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 1 +
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S| 1 +
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm  | 1 +
>  4 files changed, 4 insertions(+)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S 
> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
> index 7e1787c..8e64ce8 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
> @@ -142,6 +142,7 @@ L13:
> 
>  movl%cr0, %ebx
>  orl $0x08000, %ebx # enable paging
> +orl $0x1, %ebx # set WP
>  movl%ebx, %cr0
>  lealDSC_OFFSET(%edi),%ebx
>  movwDSC_DS(%ebx),%ax
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm 
> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
> index e6af344..a955785 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
> @@ -148,6 +148,7 @@ gSmiCr3 DD  ?
> 
>  mov ebx, cr0
>  or  ebx, 08000h ; enable paging
> +or  ebx, 1h ; set WP
>  mov cr0, ebx
>  lea ebx, [edi + DSC_OFFSET]
>  mov ax, [ebx + DSC_DS]
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S 
> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
> index 1d40819..8050a00 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
> @@ -163,6 +163,7 @@ NxeDone:
>  wrmsr
>  movq%cr0, %rbx
>  btsl$31, %ebx
> +btsl$16, %ebx   # set WP
>  movq%rbx, %cr0
>  retf
>  LongMode:   # long mode (64-bit code) starts here
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm 
> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
> index 6e1d3f1..db170d6 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
> @@ -159,6 +159,7 @@ Base:
>  wrmsr
>  mov rbx, cr0
>  bts ebx, 31
> +bts ebx, 16; set WP
>  mov cr0, rbx
>  retf
>  @LongMode:  ; long mode (64-bit code) starts here
> --
> 1.9.5.msysgit.0

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