Marking of plastic components

2002-12-09 Thread Dave Wilson

Hello Group,

I keep hearing about a requirement to mark plastic components, supposedly in 
accordance with the WEEE Directive. However, I can't find anything in the WEEE 
Directive, or the ROHS Directive. I found a reference to ISO 11469 requiring 
marking of plastic components 25g, but can't find an equivalent European 
reference. 

I also found a reference to marking of plastic packaging for waste management, 
for parts 20g, but found no European reference for that requirement either.

I scanned the emc-pstc archives but couldn't find any earlier related threads.

Can anyone clear this up?

Thanks in advance,

Dave Wilson



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Meeting Notice, Tue, 10/Dec/02, An Overview of Recent Developments in Nanotechnology

2002-12-09 Thread Hans Mellberg

Meeting Notice:

The SCV IEEE/EMC and the Product Safety Society
present:

An Overview of Recent Developments in Nanotechnology.

Time:  5:30 Social,  7:00 Presentation
Place:  Applied Materials Building 27,
3135 Kifer Road, Santa Clara CA. 

All Welcome, No entrance fee, IEEE membership not
required to attend.

We will also Vote for Officers for the Year 2003

on  Tuesday, December 10, 2002, 
Time:  5:30 Social,  7:00 Presentation

An Overview of Recent Developments in Nanotechnology

Speaker: Dr. Meyya Meyyappan, Director, Center for
Nanotechnology 
(NASA)

Abstract:  An Overview of Recent Developments in
Nanotechnology
Nanotechnology deals with creation of functional
materials, devices and
systems in the nanoscale through exploiting novel
properties 
(electrical,
physical, chemical…) arising solely due to the
nanoscale.  This is a 
broad
enabling technology with expected impact on materials
and 
manufacturing,
electronics and computing, health and medicine,
energy, transportation,
national security and space exploration.  The basic
science and 
applications
are of great deal of interest to the IEEE community. 
This talk will 
provide
an overview of novel nanoelectronics concepts based on
carbon nanotubes
(CNTs) and molecular electronics, nanosensors and
detectors,
nanoelectromechanical systems (NEMS), nanoscale
materials and 
fabrication
techniques.  Please join us and welcome Dr. Meyyappan
who will provide 
you
with a glimpse into this new exciting field of
Nanotechnology.   As 
usual,
the December meeting will include Holiday snacks.

Biography of Dr. M. Meyyappan
Dr. M. Meyyappan is the IEEE Distinguished Lecturer
for the IEEE
Nanotechnology Council.  He is the Director of the
Center for 
Nanotechnology
at NASA Ames Research Center in Moffett Field, CA. 
His Nanotechnology
center, established in 1997, consists of about 50
scientists working on
various aspects of Nanotechnology including carbon
nanotubes for
nanoelectronics, sensors and detectors, molecular
electronics, 
inorganic
nanowires for sensors and devices, protein nanotubes,
Nanotechnology in 
gene
sequencing, quantum computing, computational
Nanotechnology, 
computational
quantum electronics and optoelectronics.  His center
has strong 
academic
ties through programs for undergraduate and high
school interns, and
visiting faculty and graduate students. For further
information, please
visit the web site Web:  http://www.ipt.arc.nasa.gov

Dr. Meyyappan’s research interests include
nanoelectronics, nanodevices 
and
sensors, CVD and plasma CVD approaches for growth of
nanotubes and 
inorganic
nanowires.  He has published over 80 papers in
refereed journals 
including
25 in Nanotechnology related subjects and has given
over 50 Invited, 
Plenary
and Keynote talks and Invited seminars in the last
four years.  He is a
member of the Interagency Working Group on
Nanotechnology (IWGN), which 
is
responsible for the National Nanotechnology Initiative
(NNI). He is the 
IEEE
Nanotechnology Council Distinguished Lecturer.  He is
also the 
Conference
Chair for the IEEE Nano2003 Conference to be held in
San Francisco in 
August
2003.  He has a Ph.D. from Clarkson University and is
a member of IEEE, 
AVS,
MRS, and ECS.  He is on the Editorial Board of Journal
of Nanoscience 
and
Nanotechnology.


 Applied Materials, Bldg 27, 3135 Kifer Rd, Santa
Clara, CA



=
Best Regards
Hans T. Mellberg, Consultant
Regulatory, High Speed, EMC and Power Design Services
By the Pacific Coast next to Silicon Valley, Santa Cruz, CA, USA
office:831-454-9450, cell:408-507-9694, fax:831-454-0755
BSEE, NARTE Certified Engineer, IEEE, AIAA, dB
2004 IEEE EMC Symposium Program Chair, IEEE EMC SCV ADCOM

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prEN50731

2002-12-09 Thread Hans Mellberg

Does anyone know anything about this proposed standard? any weblinks?
Thanks in advance

Hans Mellberg

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Classification of network connections in Europe: TR 101 651 V1.1. 1 (1999-03)

2002-12-09 Thread Georgerian, Richard
Greetings All,

After reading the above standard for the classification of telecom centers,
Class 1, 2, 3 and 4, the standard references IEC 1000-2-5 to determine
types 1, 2, 3 and 4. Does anyone in the group have the short definitions
for the types from IEC 1000-2-5? The main purpose is to better understand
the characteristics and definitions of telecom centers as they relate to
Europe's central offices and customer premises. ETSI 300-386 does describe
the telecom location, but not in great detail. Other documents that describe
such telecom locations would be helpful.

Thanks.

Richard Georgerian
Compliance Engineer 
Carrier Access Corporation
5395 Pearl Parkway
Boulder, CO 80301
USA

Tele: 303-218-5748  Fax: 303-218-5503
mailto:rgeorger...@carrieraccess.com






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jobs listings Re: EMC Tech

2002-12-09 Thread paul . j . smith




For jobs,  try  listings at   http://www.nepss.org/#jobs

Regards, Paul J Smith, Teradyne




Judy Johnson judit...@shentel.net@majordomo.ieee.org on 12/08/2002
10:41:07 AM

Please respond to Judy Johnson judit...@shentel.net

Sent by:  owner-emc-p...@majordomo.ieee.org


To:   Mike Schultz mikschu...@yahoo.com, emc-p...@majordomo.ieee.org
cc:

Subject:  Re: EMC Tech



Have you looked at www.rbitem.com ?

- Original Message -
From:  Mike  Schultz
To: emc-p...@majordomo.ieee.org
Sent: Sunday, December 08, 2002 7:51  AM
Subject: EMC Tech

Seeking a position as an EMC Lab  Technician. Testing electronic products
for electromagnectic compatability to  standards such as FCC, CISPR, 
GR-1089. I am proficient in the following  tests; RDE, CDE, RDI, CDI, ESD,
EFT, Harmonics, Flicker, Surge, and  Voltage,Dips, and Sags.  5+ years
experience.  Currently living in  Raleigh, NC.  Will relocate.



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RE: Vehicle Mounted PCB

2002-12-09 Thread Price, Ed
Dave:
 
I just found a url for that vehicle EMC spec. Notice that Ford, GM  Daimler
Chrysler are setting up a lab accreditation scheme too.
 
 http://www.fordemc.com/ http://www.fordemc.com/
 
 
Ed
 
 

Ed Price 
ed.pr...@cubic.com 
Electromagnetic Compatibility Lab 
Cubic Defense Systems 
San Diego, CA  USA 
858-505-2780  (Voice) 
858-505-1583  (Fax) 
Military  Avionics EMC Is Our Specialty 
Shake-Bake-Shock - Metrology - Reliability Analysis 

-Original Message-
From: David Sproul [mailto:david.spr...@alexanderlynn.co.uk]
Sent: Monday, December 09, 2002 2:57 AM
To: EMC-PSTC
Subject: Vehicle Mounted PCB


Thanks to all those who responded to my posting.  
 
Some responses were helpful, some were amusing, and some were both, but all
were gladly received.
 
Best regards,
David Sproul,
 



EMC Retesting

2002-12-09 Thread White, Ian
Hi
 
Thanks to all those who responded.
 
Regards
 
Ian White
(Spirax Sarco Ltd)
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RE: anechoic EMC testing chambers for sale

2002-12-09 Thread Michael Taylor
You might try Scott Hagel @ Scientific Hardware, a wizard with chambers, he
may have interest.  That's his business.
He's in Gilroy, CA at 408-848-8868 or fax 408-848-8878.

-Original Message-
From: paul.j.sm...@teradyne.com [mailto:paul.j.sm...@teradyne.com]
Sent: Friday, December 06, 2002 2:55 PM
To: emc-p...@majordomo.ieee.org
Subject: Re: anechoic EMC testing chambers for sale




Folks

Due to a facility closings I need a plan within two weeks
to remove a 32 ft by 38 ft by 10 ft  anechoic EMC testing chamber
which is currently installed, calibrated and accredited in CA.

I also have a 14 ft by 24 ft by 10 ft 10 ft  anechoic EMC testing chamber
which is currently in storage in MA from a previous facility closing.

Please contact John Freudenberg directly at
john.freudenb...@teradyne.com if you have any ideas.

ThanksPaul S



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RE: PCBA Inspection Stamps

2002-12-09 Thread Roman, Dan

Doug,

You could attach a process tag that goes with the board and have the
inspectors and testers stamp that instead.  I'm sure you could make your
manufacturing processes accommodate the change and still maintain
traceability.  The product at the customer's site does not need the stamps
on the PCB, you just need to maintain traceability during your manufacturing
process.

Just one low-tech option I'm sure.

Dan

-Original Message-
From: POWELL, DOUG [mailto:doug.pow...@aei.com]
Sent: Friday, December 06, 2002 6:03 PM
To: EMC-PSTC (E-mail)
Subject: PCBA Inspection Stamps



Hello group,

I have a request for information on stamping methods of PCBAs.  I would
normally post this question on one of the discussion forums for PCB design,
but this question really does pertain to product safety.  But first, please
indulge me while I provide a little background information...

My company uses a very large number of PCB assemblies with wide variety of
technologies.  Many of these boards have safety considerations and receive
routine hipot testing during manufacture.  As is normally the case, in-house
and outsource assembly of the boards requires various kinds of inspection
and test with stamps for validation.  Traditionally these are rubber stamps
or some form of an adhesive label with printing.   Many of our boards have
high voltage separation from SELV circuits and as it turns out the most
convenient place to put a stamp is in a safety keepout zone.  There have
been a number of hipot failures that track right through this stamp.  In our
standard practices manual, we specify the use of only white epoxy based
inks, but some of these are conductive as well.  In addition, with the ever
shrinking geometries of high density boards, placing a nonconductive stamp
on a low voltage circuit interferes by insulating test points for bed of
nails testing.   Since inspection marks are usually placed by hand, the
faults we see are fairly random.   So, on the one hand conductive inks are
bad and on the other hand nonconductive inks are bad.

In an effort to solve this problem, we've considered providing a
silk-screened area of the board  that is safe to stamp, but real estate is
now at a premium and solder-side silk costs on average about 10% more.
Plus, it won't be long until computerized component ID and location
eliminates the need for silk-screen entirely.  

My question is this:  Has anyone discovered a technology or process of any
sort, for marking of ultra-high density or high voltage PCBAs and is easy to
implement in most board houses?  I have to think that with all the
technological advances the old rubber stamp or adhesive label could be
replaced somehow.  Who knows, maybe some form of UV identification?

I am very interested to hear any success stories that you may have.

Best regards to all,

-doug

Douglas E. Powell
Compliance Engineer
Advanced Energy Industries, Inc.
Fort Collins, CO 80535 USA



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Vehicle Mounted PCB

2002-12-09 Thread David Sproul
Thanks to all those who responded to my posting.

Some responses were helpful, some were amusing, and some were both, but all
were gladly received.

Best regards,
David Sproul,



Re: excessive crosstalk

2002-12-09 Thread John Woodgate

I read in !emc-pstc that Doug Smith d...@emcesd.com wrote (in
3df40e44.2050...@emcesd.com) about 'excessive crosstalk' on Sun, 8 Dec
2002:
Right above that you 
will find a link to pictures from the latest IEC TC77b meeting.

Any pictures from the SC77B meeting? (;-)

There's enough confusion about standards without munging the committee
references, IMHO.
-- 
Regards, John Woodgate, OOO - Own Opinions Only. http://www.jmwa.demon.co.uk 
Interested in professional sound reinforcement and distribution? Then go to 
http://www.isce.org.uk
PLEASE do NOT copy news posts to me by E-MAIL!

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excessive crosstalk

2002-12-09 Thread Doug Smith


Hi All,

It's time for another short tech article

Many of us in in the technical community know that crossing a path 
over a break in the ground/power planes on a board can have 
undesirable effects. One effect sometimes overlooked is excessive 
crosstalk that occurs between paths crossing the break. December's 
Technical Tidbit on my site at http://emcesd.com titled Crossing 
Ground Plane Breaks, A Source of Crosstalk presents measured data 
that shows the crosstalk, even that due to a short break in a ground 
plane, can be signficant.


There is lots of stuff in the middle, but if you page down to the 
bottom of the page you will see the link to the article in the form of 
a picture of a circuit board with a ground slit. Right above that you 
will find a link to pictures from the latest IEC TC77b meeting.


Doug
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