Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
ping flow gg 于2024年3月3日周日 23:03写道： > Sorry since I did not send the emails all at once, so cannot apply all 4 > patches together with git am *.patch. Instead, it needs to first apply the > patch with 'git am '[PATCH] lavc/vp8dsp: R-V V put_vp8_pixels'', and then > apply the patches 1-3 in the series with 'git am *.patch'. > > Rémi Denis-Courmont 于2024年3月3日周日 22:39写道： > >> Le perjantaina 23. helmikuuta 2024, 16.45.46 EET flow gg a écrit : >> > >> >> Looks like this needs rebasing, or otherwise does not apply. >> >> -- >> Rémi Denis-Courmont >> http://www.remlab.net/ >> >> >> >> ___ >> ffmpeg-devel mailing list >> ffmpeg-devel@ffmpeg.org >> https://ffmpeg.org/mailman/listinfo/ffmpeg-devel >> >> To unsubscribe, visit link above, or email >> ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". >> > ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
Sorry since I did not send the emails all at once, so cannot apply all 4 patches together with git am *.patch. Instead, it needs to first apply the patch with 'git am '[PATCH] lavc/vp8dsp: R-V V put_vp8_pixels'', and then apply the patches 1-3 in the series with 'git am *.patch'. Rémi Denis-Courmont 于2024年3月3日周日 22:39写道： > Le perjantaina 23. helmikuuta 2024, 16.45.46 EET flow gg a écrit : > > > > Looks like this needs rebasing, or otherwise does not apply. > > -- > Rémi Denis-Courmont > http://www.remlab.net/ > > > > ___ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". > ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
Le perjantaina 23. helmikuuta 2024, 16.45.46 EET flow gg a écrit : > Looks like this needs rebasing, or otherwise does not apply. -- Rémi Denis-Courmont http://www.remlab.net/ ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
Le lauantaina 24. helmikuuta 2024, 10.31.36 EET flow gg a écrit : > Okay, Thanks for clarifying. > > I have used many fractional multipliers, mostly not for correctness, but > often for performance improvements (though I don't know why), > and there are no obvious downsides, How about leaving this code? In this case, it does not affect the baseline requirements. It will be problematic if performance ends up worse on other future designs, but we can cross that bridge if and then. -- レミ・デニ-クールモン http://www.remlab.net/ ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
Okay, Thanks for clarifying. I have used many fractional multipliers, mostly not for correctness, but often for performance improvements (though I don't know why), and there are no obvious downsides, How about leaving this code? Rémi Denis-Courmont 于2024年2月24日周六 15:39写道： > Hi, > > Le 24 février 2024 03:07:36 GMT+02:00, flow gg a > écrit : > > .ifc \len,4 > >-vsetivlizero, 5, e8, mf2, ta, ma > >+vsetivlizero, 5, e8, m1, ta, ma > > .elseif \len == 8 > > vsetivlizero, 9, e8, m1, ta, ma > > .else > >@@ -112,9 +112,9 @@ endfunc > > vslide1down.vx v2, \dst, t5 > > > > .ifc \len,4 > >-vsetivlizero, 4, e8, mf4, ta, ma > >+vsetivlizero, 4, e8, m1, ta, ma > > .elseif \len == 8 > >-vsetivlizero, 8, e8, mf2, ta, ma > >+vsetivlizero, 8, e8, m1, ta, ma > > > >What are the benefits of not using fractional multipliers here? > > Insofar as E8/MF4 is guaranteed to work for Zve32x, there are no benefits > per se. > > However fractional multipliers were added to the specification to enable > addressing invididual vectors whilst the effective multiplier is larger > than one. This can only happen with mixed widths. Fractions were not > intended to make vector shorter - there is the vector length for that > already. > > That's why "E64/MF2" doesn't work, even though it's the same vector bit > size as "E8/MF2". > > > Making this > >change would result in a 10%-20% slowdown. > > That's kind of odd. This may be caused by the slides, but it's strange to > go out of the way for hardware to optimise a case that's not even intended. > > > mf2/4 m1 > >vp8_put_bilin4_h_rvv_i32: 158.7 193.7 > >vp8_put_bilin4_hv_rvv_i32: 255.7 302.7 > >vp8_put_bilin8_h_rvv_i32: 318.7 358.7 > >vp8_put_bilin8_hv_rvv_i32: 528.7 569.7 > > > >Rémi Denis-Courmont 于2024年2月24日周六 01:18写道： > > > >> Hi, > >> > >> + > >> +.macro bilin_h_load dst len > >> +.ifc \len,4 > >> +vsetivlizero, 5, e8, mf2, ta, ma > >> > >> Don't use fractional multipliers if you don't mix element widths. > >> > >> +.elseif \len == 8 > >> +vsetivlizero, 9, e8, m1, ta, ma > >> +.else > >> +vsetivlizero, 17, e8, m2, ta, ma > >> +.endif > >> + > >> +vle8.v \dst, (a2) > >> +vslide1down.vx v2, \dst, t5 > >> + > >> > >> +.ifc \len,4 > >> +vsetivlizero, 4, e8, mf4, ta, ma > >> > >> Same as above. > >> > >> +.elseif \len == 8 > >> +vsetivlizero, 8, e8, mf2, ta, ma > >> > >> Also. > >> > >> +.else > >> +vsetivlizero, 16, e8, m1, ta, ma > >> +.endif > >> > >> +vwmulu.vx v28, \dst, t1 > >> +vwmaccu.vx v28, a5, v2 > >> +vwaddu.wx v24, v28, t4 > >> +vnsra.wi\dst, v24, 3 > >> +.endm > >> + > >> +.macro put_vp8_bilin_h len > >> +li t1, 8 > >> +li t4, 4 > >> +li t5, 1 > >> +sub t1, t1, a5 > >> +1: > >> +addia4, a4, -1 > >> +bilin_h_loadv0, \len > >> +vse8.v v0, (a0) > >> +add a2, a2, a3 > >> +add a0, a0, a1 > >> +bneza4, 1b > >> + > >> +ret > >> +.endm > >> + > >> +func ff_put_vp8_bilin16_h_rvv, zve32x > >> +put_vp8_bilin_h 16 > >> +endfunc > >> + > >> +func ff_put_vp8_bilin8_h_rvv, zve32x > >> +put_vp8_bilin_h 8 > >> +endfunc > >> + > >> +func ff_put_vp8_bilin4_h_rvv, zve32x > >> +put_vp8_bilin_h 4 > >> +endfunc > >> > >> -- > >> レミ・デニ-クールモン > >> http://www.remlab.net/ > >> > >> > >> > >> ___ > >> ffmpeg-devel mailing list > >> ffmpeg-devel@ffmpeg.org > >> https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > >> > >> To unsubscribe, visit link above, or email > >> ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". > >> > >___ > >ffmpeg-devel mailing list > >ffmpeg-devel@ffmpeg.org > >https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > > >To unsubscribe, visit link above, or email > >ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". > ___ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". > ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
Hi, Le 24 février 2024 03:07:36 GMT+02:00, flow gg a écrit : > .ifc \len,4 >-vsetivlizero, 5, e8, mf2, ta, ma >+vsetivlizero, 5, e8, m1, ta, ma > .elseif \len == 8 > vsetivlizero, 9, e8, m1, ta, ma > .else >@@ -112,9 +112,9 @@ endfunc > vslide1down.vx v2, \dst, t5 > > .ifc \len,4 >-vsetivlizero, 4, e8, mf4, ta, ma >+vsetivlizero, 4, e8, m1, ta, ma > .elseif \len == 8 >-vsetivlizero, 8, e8, mf2, ta, ma >+vsetivlizero, 8, e8, m1, ta, ma > >What are the benefits of not using fractional multipliers here? Insofar as E8/MF4 is guaranteed to work for Zve32x, there are no benefits per se. However fractional multipliers were added to the specification to enable addressing invididual vectors whilst the effective multiplier is larger than one. This can only happen with mixed widths. Fractions were not intended to make vector shorter - there is the vector length for that already. That's why "E64/MF2" doesn't work, even though it's the same vector bit size as "E8/MF2". > Making this >change would result in a 10%-20% slowdown. That's kind of odd. This may be caused by the slides, but it's strange to go out of the way for hardware to optimise a case that's not even intended. > mf2/4 m1 >vp8_put_bilin4_h_rvv_i32: 158.7 193.7 >vp8_put_bilin4_hv_rvv_i32: 255.7 302.7 >vp8_put_bilin8_h_rvv_i32: 318.7 358.7 >vp8_put_bilin8_hv_rvv_i32: 528.7 569.7 > >Rémi Denis-Courmont 于2024年2月24日周六 01:18写道： > >> Hi, >> >> + >> +.macro bilin_h_load dst len >> +.ifc \len,4 >> +vsetivlizero, 5, e8, mf2, ta, ma >> >> Don't use fractional multipliers if you don't mix element widths. >> >> +.elseif \len == 8 >> +vsetivlizero, 9, e8, m1, ta, ma >> +.else >> +vsetivlizero, 17, e8, m2, ta, ma >> +.endif >> + >> +vle8.v \dst, (a2) >> +vslide1down.vx v2, \dst, t5 >> + >> >> +.ifc \len,4 >> +vsetivlizero, 4, e8, mf4, ta, ma >> >> Same as above. >> >> +.elseif \len == 8 >> +vsetivlizero, 8, e8, mf2, ta, ma >> >> Also. >> >> +.else >> +vsetivlizero, 16, e8, m1, ta, ma >> +.endif >> >> +vwmulu.vx v28, \dst, t1 >> +vwmaccu.vx v28, a5, v2 >> +vwaddu.wx v24, v28, t4 >> +vnsra.wi\dst, v24, 3 >> +.endm >> + >> +.macro put_vp8_bilin_h len >> +li t1, 8 >> +li t4, 4 >> +li t5, 1 >> +sub t1, t1, a5 >> +1: >> +addia4, a4, -1 >> +bilin_h_loadv0, \len >> +vse8.v v0, (a0) >> +add a2, a2, a3 >> +add a0, a0, a1 >> +bneza4, 1b >> + >> +ret >> +.endm >> + >> +func ff_put_vp8_bilin16_h_rvv, zve32x >> +put_vp8_bilin_h 16 >> +endfunc >> + >> +func ff_put_vp8_bilin8_h_rvv, zve32x >> +put_vp8_bilin_h 8 >> +endfunc >> + >> +func ff_put_vp8_bilin4_h_rvv, zve32x >> +put_vp8_bilin_h 4 >> +endfunc >> >> -- >> レミ・デニ-クールモン >> http://www.remlab.net/ >> >> >> >> ___ >> ffmpeg-devel mailing list >> ffmpeg-devel@ffmpeg.org >> https://ffmpeg.org/mailman/listinfo/ffmpeg-devel >> >> To unsubscribe, visit link above, or email >> ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". >> >___ >ffmpeg-devel mailing list >ffmpeg-devel@ffmpeg.org >https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > >To unsubscribe, visit link above, or email >ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
.ifc \len,4 -vsetivlizero, 5, e8, mf2, ta, ma +vsetivlizero, 5, e8, m1, ta, ma .elseif \len == 8 vsetivlizero, 9, e8, m1, ta, ma .else @@ -112,9 +112,9 @@ endfunc vslide1down.vx v2, \dst, t5 .ifc \len,4 -vsetivlizero, 4, e8, mf4, ta, ma +vsetivlizero, 4, e8, m1, ta, ma .elseif \len == 8 -vsetivlizero, 8, e8, mf2, ta, ma +vsetivlizero, 8, e8, m1, ta, ma What are the benefits of not using fractional multipliers here? Making this change would result in a 10%-20% slowdown. mf2/4 m1 vp8_put_bilin4_h_rvv_i32: 158.7 193.7 vp8_put_bilin4_hv_rvv_i32: 255.7 302.7 vp8_put_bilin8_h_rvv_i32: 318.7 358.7 vp8_put_bilin8_hv_rvv_i32: 528.7 569.7 Rémi Denis-Courmont 于2024年2月24日周六 01:18写道： > Hi, > > + > +.macro bilin_h_load dst len > +.ifc \len,4 > +vsetivlizero, 5, e8, mf2, ta, ma > > Don't use fractional multipliers if you don't mix element widths. > > +.elseif \len == 8 > +vsetivlizero, 9, e8, m1, ta, ma > +.else > +vsetivlizero, 17, e8, m2, ta, ma > +.endif > + > +vle8.v \dst, (a2) > +vslide1down.vx v2, \dst, t5 > + > > +.ifc \len,4 > +vsetivlizero, 4, e8, mf4, ta, ma > > Same as above. > > +.elseif \len == 8 > +vsetivlizero, 8, e8, mf2, ta, ma > > Also. > > +.else > +vsetivlizero, 16, e8, m1, ta, ma > +.endif > > +vwmulu.vx v28, \dst, t1 > +vwmaccu.vx v28, a5, v2 > +vwaddu.wx v24, v28, t4 > +vnsra.wi\dst, v24, 3 > +.endm > + > +.macro put_vp8_bilin_h len > +li t1, 8 > +li t4, 4 > +li t5, 1 > +sub t1, t1, a5 > +1: > +addia4, a4, -1 > +bilin_h_loadv0, \len > +vse8.v v0, (a0) > +add a2, a2, a3 > +add a0, a0, a1 > +bneza4, 1b > + > +ret > +.endm > + > +func ff_put_vp8_bilin16_h_rvv, zve32x > +put_vp8_bilin_h 16 > +endfunc > + > +func ff_put_vp8_bilin8_h_rvv, zve32x > +put_vp8_bilin_h 8 > +endfunc > + > +func ff_put_vp8_bilin4_h_rvv, zve32x > +put_vp8_bilin_h 4 > +endfunc > > -- > レミ・デニ-クールモン > http://www.remlab.net/ > > > > ___ > ffmpeg-devel mailing list > ffmpeg-devel@ffmpeg.org > https://ffmpeg.org/mailman/listinfo/ffmpeg-devel > > To unsubscribe, visit link above, or email > ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe". > ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
Re: [FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
Hi, + +.macro bilin_h_load dst len +.ifc \len,4 +vsetivlizero, 5, e8, mf2, ta, ma Don't use fractional multipliers if you don't mix element widths. +.elseif \len == 8 +vsetivlizero, 9, e8, m1, ta, ma +.else +vsetivlizero, 17, e8, m2, ta, ma +.endif + +vle8.v \dst, (a2) +vslide1down.vx v2, \dst, t5 + +.ifc \len,4 +vsetivlizero, 4, e8, mf4, ta, ma Same as above. +.elseif \len == 8 +vsetivlizero, 8, e8, mf2, ta, ma Also. +.else +vsetivlizero, 16, e8, m1, ta, ma +.endif +vwmulu.vx v28, \dst, t1 +vwmaccu.vx v28, a5, v2 +vwaddu.wx v24, v28, t4 +vnsra.wi\dst, v24, 3 +.endm + +.macro put_vp8_bilin_h len +li t1, 8 +li t4, 4 +li t5, 1 +sub t1, t1, a5 +1: +addia4, a4, -1 +bilin_h_loadv0, \len +vse8.v v0, (a0) +add a2, a2, a3 +add a0, a0, a1 +bneza4, 1b + +ret +.endm + +func ff_put_vp8_bilin16_h_rvv, zve32x +put_vp8_bilin_h 16 +endfunc + +func ff_put_vp8_bilin8_h_rvv, zve32x +put_vp8_bilin_h 8 +endfunc + +func ff_put_vp8_bilin4_h_rvv, zve32x +put_vp8_bilin_h 4 +endfunc -- レミ・デニ-クールモン http://www.remlab.net/ ___ ffmpeg-devel mailing list ffmpeg-devel@ffmpeg.org https://ffmpeg.org/mailman/listinfo/ffmpeg-devel To unsubscribe, visit link above, or email ffmpeg-devel-requ...@ffmpeg.org with subject "unsubscribe".
[FFmpeg-devel] [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
From b773a2b640ba38a106539da7f3414d6892364c4f Mon Sep 17 00:00:00 2001
From: sunyuechi
Date: Fri, 23 Feb 2024 13:27:42 +0800
Subject: [PATCH 1/3] lavc/vp8dsp: R-V V put_bilin_h
C908:
vp8_put_bilin4_h_c: 373.5
vp8_put_bilin4_h_rvv_i32: 158.7
vp8_put_bilin8_h_c: 1437.7
vp8_put_bilin8_h_rvv_i32: 318.7
vp8_put_bilin16_h_c: 2845.7
vp8_put_bilin16_h_rvv_i32: 374.7
---
libavcodec/riscv/vp8dsp_init.c | 11 +++
libavcodec/riscv/vp8dsp_rvv.S | 54 ++
2 files changed, 65 insertions(+)
diff --git a/libavcodec/riscv/vp8dsp_init.c b/libavcodec/riscv/vp8dsp_init.c
index c364de3dc9..32cb4893a4 100644
--- a/libavcodec/riscv/vp8dsp_init.c
+++ b/libavcodec/riscv/vp8dsp_init.c
@@ -34,6 +34,10 @@ VP8_EPEL(16, rvv);
VP8_EPEL(8, rvv);
VP8_EPEL(4, rvv);
+VP8_BILIN(16, rvv);
+VP8_BILIN(8, rvv);
+VP8_BILIN(4, rvv);
+
av_cold void ff_vp78dsp_init_riscv(VP8DSPContext *c)
{
#if HAVE_RVV
@@ -47,6 +51,13 @@ av_cold void ff_vp78dsp_init_riscv(VP8DSPContext *c)
c->put_vp8_bilinear_pixels_tab[0][0][0] = ff_put_vp8_pixels16_rvv;
c->put_vp8_bilinear_pixels_tab[1][0][0] = ff_put_vp8_pixels8_rvv;
c->put_vp8_bilinear_pixels_tab[2][0][0] = ff_put_vp8_pixels4_rvv;
+
+c->put_vp8_bilinear_pixels_tab[0][0][1] = ff_put_vp8_bilin16_h_rvv;
+c->put_vp8_bilinear_pixels_tab[0][0][2] = ff_put_vp8_bilin16_h_rvv;
+c->put_vp8_bilinear_pixels_tab[1][0][1] = ff_put_vp8_bilin8_h_rvv;
+c->put_vp8_bilinear_pixels_tab[1][0][2] = ff_put_vp8_bilin8_h_rvv;
+c->put_vp8_bilinear_pixels_tab[2][0][1] = ff_put_vp8_bilin4_h_rvv;
+c->put_vp8_bilinear_pixels_tab[2][0][2] = ff_put_vp8_bilin4_h_rvv;
}
#endif
}
diff --git a/libavcodec/riscv/vp8dsp_rvv.S b/libavcodec/riscv/vp8dsp_rvv.S
index 063ab7110c..c8d265e516 100644
--- a/libavcodec/riscv/vp8dsp_rvv.S
+++ b/libavcodec/riscv/vp8dsp_rvv.S
@@ -98,3 +98,57 @@ func ff_put_vp8_pixels4_rvv, zve32x
vsetivli zero, 4, e8, mf4, ta, ma
put_vp8_pixels
endfunc
+
+.macro bilin_h_load dst len
+.ifc \len,4
+vsetivlizero, 5, e8, mf2, ta, ma
+.elseif \len == 8
+vsetivlizero, 9, e8, m1, ta, ma
+.else
+vsetivlizero, 17, e8, m2, ta, ma
+.endif
+
+vle8.v \dst, (a2)
+vslide1down.vx v2, \dst, t5
+
+.ifc \len,4
+vsetivlizero, 4, e8, mf4, ta, ma
+.elseif \len == 8
+vsetivlizero, 8, e8, mf2, ta, ma
+.else
+vsetivlizero, 16, e8, m1, ta, ma
+.endif
+
+vwmulu.vx v28, \dst, t1
+vwmaccu.vx v28, a5, v2
+vwaddu.wx v24, v28, t4
+vnsra.wi\dst, v24, 3
+.endm
+
+.macro put_vp8_bilin_h len
+li t1, 8
+li t4, 4
+li t5, 1
+sub t1, t1, a5
+1:
+addia4, a4, -1
+bilin_h_loadv0, \len
+vse8.v v0, (a0)
+add a2, a2, a3
+add a0, a0, a1
+bneza4, 1b
+
+ret
+.endm
+
+func ff_put_vp8_bilin16_h_rvv, zve32x
+put_vp8_bilin_h 16
+endfunc
+
+func ff_put_vp8_bilin8_h_rvv, zve32x
+put_vp8_bilin_h 8
+endfunc
+
+func ff_put_vp8_bilin4_h_rvv, zve32x
+put_vp8_bilin_h 4
+endfunc
--
2.43.2
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