flashrom on Linux 4.18.18-041818-generic (x86_64)
flashrom was built with libpci 3.5.2, GCC 7.3.0, little endian
Command line (5 args): flashrom --programmer internal -V -o result.txt
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
/sys/class/mtd/mtd0 does not exist
No coreboot table found.
Using Internal DMI decoder.
DMI string chassis-type: "Desktop"
DMI string system-manufacturer: "Gigabyte Technology Co., Ltd."
DMI string system-product-name: "Z97-HD3"
DMI string system-version: "To be filled by O.E.M."
DMI string baseboard-manufacturer: "Gigabyte Technology Co., Ltd."
DMI string baseboard-product-name: "Z97-HD3"
DMI string baseboard-version: "x.x"
Found ITE Super I/O, ID 0x8620 on port 0x2e
Found chipset "Intel Z97" with PCI ID 8086:8cc4.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware
with it,
then please email a report to flashrom@flashrom.org including a verbose
(-V) log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0xc65: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap: not enabled
0xfff8/0xffb8 FWH IDSEL: 0x0
0xfff0/0xffb0 FWH IDSEL: 0x0
0xffe8/0xffa8 FWH IDSEL: 0x1
0xffe0/0xffa0 FWH IDSEL: 0x1
0xffd8/0xff98 FWH IDSEL: 0x2
0xffd0/0xff90 FWH IDSEL: 0x2
0xffc8/0xff88 FWH IDSEL: 0x3
0xffc0/0xff80 FWH IDSEL: 0x3
0xff70/0xff30 FWH IDSEL: 0x4
0xff60/0xff20 FWH IDSEL: 0x5
0xff50/0xff10 FWH IDSEL: 0x6
0xff40/0xff00 FWH IDSEL: 0x7
0xfff8/0xffb8 FWH decode enabled
0xfff0/0xffb0 FWH decode enabled
0xffe8/0xffa8 FWH decode enabled
0xffe0/0xffa0 FWH decode enabled
0xffd8/0xff98 FWH decode enabled
0xffd0/0xff90 FWH decode enabled
0xffc8/0xff88 FWH decode enabled
0xffc0/0xff80 FWH decode enabled
0xff70/0xff30 FWH decode enabled
0xff60/0xff20 FWH decode enabled
0xff50/0xff10 FWH decode enabled
0xff40/0xff00 FWH decode enabled
Maximum FWH chip size: 0x10 bytes
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x7f3d65a61000 + 0x3800
0x04: 0xf008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
SPI Configuration is locked down.
Reading OPCODES... done
OP Type Pre-OP
op[0]: 0x02, write w/ addr, none
op[1]: 0x3b, read w/ addr, none
op[2]: 0x20, write w/ addr, none
op[3]: 0x05, read w/o addr, none
op[4]: 0x9f, read w/o addr, none
op[5]: 0x01, write w/o addr, none
op[6]: 0x00, read w/o addr, none
op[7]: 0x00, read w/o addr, none
Pre-OP 0: 0x06, Pre-OP 1: 0x00
0x06: 0x (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
0x08: 0x (FADDR)
0x50: 0x (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff
0x54: 0x FREG0: Flash Descriptor region (0x-0x0fff)
is read-write.
0x58: 0x07ff FREG1: BIOS region (0x-0x007f) is read-write.
0x5C: 0x01ff0001 FREG2: Management Engine region (0x1000-0x001f)
is read-write.
0x60: 0x7fff FREG3: Gigabit Ethernet region is unused.
0x64: 0x7fff FREG4: Platform Data region is unused.
0x74: 0x (PR0 is unused)
0x78: 0x (PR1 is unused)
0x7C: 0x (PR2 is unused)
0x80: 0x (PR3 is unused)
0x84: 0x (PR4 is unused)
0x90: 0xc0 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0x91: 0xfc4010 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=0, SME=0, SCF=4
0x94: 0x0006 (PREOP)
0x96: 0x043b (OPTYPE)
0x98: 0x05203b02 (OPMENU)
0x9c: 0x019f (OPMENU+4)
0xA0: 0x (BBAR)
0xC4: 0x80802045 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xC8: 0x2045 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
0xD0: 0x50444653 (FPB)
Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0 0x02040003
FLMAP1 0x15100206
FLMAP2 0x26210120
--- Details ---
NR (Number of Regions): 3
FRBA (Flash Region Base Address): 0x040
NC (Number of Components): 1
FCBA (Flash Component Base Address): 0x030
ISL (ICH/PCH Strap Length): 21
FISBA/FPSBA (Flash ICH/PCH Strap Base Address): 0x100
NM (Number of Masters): 3
FMBA (Flash Master Base Address): 0x060
MSL/PSL (MCH/PROC Strap Length): 1
FMSBA (Flash MCH/PROC Strap Base Address): 0x200
=== Component Section ===
FLCOMP 0x64900044
FLILL 0xad604221
--- Details ---
Component 1 density: 8 MB
Component 2 is not used.
Read Clock Frequency: 20 MHz
Read ID and Status Clock Freq.: 50 MHz
Write and Erase Clock Freq.: 50 MHz
Fast Read is
