Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
I did have a look at mips-opc.c in binutils, this looks easy to parse, I will give this a try, thank you for the hint! I will come back to you with a 2nd version, looks like a nice task to complete while sitting in the train Michael Am 17.06.13 08:12, schrieb Sergei Gorelkin: 16.06.2013 22:17, Michael Ring пишет: I have now browsed through the current mips documentation and have created a file that includes all opcodes, the version they are first in (starting with mips32) and a small comment what the mnemonic does. This file is attached to this mail. The problem here is that MIPS32 is not the first, but fifth version of MIPS instruction sets, preceded by MIPS I, MIPS II, MIPS III and MIPS IV. Currently there is no separation between instructions sets in compiler sources, but they need to appear one day. MIPS32 documentation is not correct in this respect, as it says e.g. that ADD is first supported by MIPS32, while it is actually MIPS I instruction. The most accurate source is probably the GNU Opcode library, which is part of binutils. Out of this file it is easy to create both compiler/mips/strinst.inc and compiler/mips/opcode.inc. Now I am looking for additional lines that I will need to add to this file, to find out what is necessary I have created a list of mnemonics that exist only in the original opcode.inc file (see later) there are a number of entries in the form xxx64xxx and xxx32, xxxg and dxxx, all those do not seem to be valid for mips32 up, where do those come from and which of those do I need to add? xxx64xxx and xxxg are likely subject for removal, I've no idea where they came from. dxxx and xxx32 are MIPS III instructions, as well as sdr,sdl,lwu and alike. A lot of other stuff (la, li, neg, mulo, seq, etc.) are macros that are expanded into several instructions. There's one very strange entry in opcode.inc: 'b ' there is also 'b', is it necessary to have 'b ' ? The codegenerator and optimizer expect conditional and unconditional branches to have distinct opcodes, this strange construction provides that. Regards, Sergei ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
16.06.2013 22:17, Michael Ring пишет: I have now browsed through the current mips documentation and have created a file that includes all opcodes, the version they are first in (starting with mips32) and a small comment what the mnemonic does. This file is attached to this mail. The problem here is that MIPS32 is not the first, but fifth version of MIPS instruction sets, preceded by MIPS I, MIPS II, MIPS III and MIPS IV. Currently there is no separation between instructions sets in compiler sources, but they need to appear one day. MIPS32 documentation is not correct in this respect, as it says e.g. that ADD is first supported by MIPS32, while it is actually MIPS I instruction. The most accurate source is probably the GNU Opcode library, which is part of binutils. Out of this file it is easy to create both compiler/mips/strinst.inc and compiler/mips/opcode.inc. Now I am looking for additional lines that I will need to add to this file, to find out what is necessary I have created a list of mnemonics that exist only in the original opcode.inc file (see later) there are a number of entries in the form xxx64xxx and xxx32, xxxg and dxxx, all those do not seem to be valid for mips32 up, where do those come from and which of those do I need to add? xxx64xxx and xxxg are likely subject for removal, I've no idea where they came from. dxxx and xxx32 are MIPS III instructions, as well as sdr,sdl,lwu and alike. A lot of other stuff (la, li, neg, mulo, seq, etc.) are macros that are expanded into several instructions. There's one very strange entry in opcode.inc: 'b ' there is also 'b', is it necessary to have 'b ' ? The codegenerator and optimizer expect conditional and unconditional branches to have distinct opcodes, this strange construction provides that. Regards, Sergei ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
I have now browsed through the current mips documentation and have
created a file that includes all opcodes, the version they are first in
(starting with mips32) and a small comment what the mnemonic does.
This file is attached to this mail.
Out of this file it is easy to create both compiler/mips/strinst.inc and
compiler/mips/opcode.inc.
Now I am looking for additional lines that I will need to add to this
file, to find out what is necessary I have created a list of mnemonics
that exist only in the original opcode.inc file (see later)
there are a number of entries in the form xxx64xxx and xxx32, xxxg and
dxxx, all those do not seem to be valid for mips32 up, where do those
come from and which of those do I need to add?
There's one very strange entry in opcode.inc: 'b '
there is also 'b', is it necessary to have 'b ' ?
Thank you,
Michael
'add64sub',
'b ',
'dadd',
'daddi',
'daddiu',
'daddu',
'ddiv',
'ddivg',
'ddivu',
'ddivug',
'div64sub',
'divg',
'divug',
'dli',
'dmfc1',
'dmodg',
'dmodug',
'dmtc1',
'dmul',
'dmulo',
'dmulou',
'dmult',
'dmultg',
'dmultu',
'dmultug',
'dneg',
'dnegu',
'drem',
'dremu',
'dsll',
'dsll32',
'dsllv',
'dsra',
'dsra32',
'dsrav',
'dsrl',
'dsrl32',
'dsrlv',
'dsub',
'dsubu',
'end_def'
'la',
'ld',
'ldl',
'ldr',
'li',
'lld',
'lwu',
'modg',
'modug',
'move',
'mul64sub',
'mulo',
'mulou',
'multg',
'multug',
'neg',
'neg64sub',
'negu',
'not',
'not64sub',
'or64sub',
'rem',
'remu',
'sar64sub',
'scd',
'sd',
'sdl',
'sdr',
'seq',
'sge',
'sgeu',
'sgt',
'sgtu',
'shl64sub',
'shr64sub',
'sle',
'sleu',
'sne',
'sub64sub',
'xor64sub',
Am 05.06.13 20:23, schrieb Michael Ring:
Thank you, the startup code is compiling now, I will send you a patch
with the missing opcodes to have full support of mips32r2 soon.
Michael
Am 03.06.13 22:04, schrieb Sergei Gorelkin:
29.05.2013 21:44, Michael Ring пишет:
This is looking good now on first view, all statements seem to pass
through now.
The only thing not working is the register error in mfc0 (and
friends) command.
Now I will wade through some more code to find out why my nice param
-CpMIPS32R2 is ignored by
assembler, it still defaults to MIPS2:
I hopefully fixed this issue in r24643, and the register naming issue
in r24799.
Should you encounter more issues, do not hesitate to report them.
Regards,
Sergei
___
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// Translate this file with the following commands:
// cat opcodestrinst.txt | grep -v ^// | grep -v ^$ | awk -F\| '{ print
A_ $1 , // $3 }' | sed -e s,\.,_,g opcode.inc
// cat opcodestrinst.txt | grep -v ^// | grep -v ^$ | sed -e s,^P_,.,g
-e s,.SET,p_set,g | awk -F\| '{ print ^ $1 ^, // $3 }' | tr '[:upper:]'
'[:lower:]' | sed s,\^,\',g strinst.inc
//Assembler specific Commands
NONE|PRE|none
P_SET_NOMIPS16|PRE|nomips16
P_SET_NOREORDER|PRE|noreorder
P_SET_NOMACRO|PRE|nomacro
P_SET_MACRO|PRE|macro
P_SET_REORDER|PRE|set_reorder
P_SET_NOAT|PRE|set_noat
P_SET_AT|PRE|set_at
P_FRAME|PRE|frame
P_MASK|PRE|mask
P_FMASK|PRE|fmask
P_CPLOAD|PRE|cpload
P_CPRESTORE|PRE|cprestore
P_CPADD|PRE|cpadd
//CPU Arithmetic Instructions
ADD|MIPS32|Add Word
ADDI|MIPS32|Add Immediate Word
ADDIU|MIPS32|Add Immediate Unsigned Word
ADDU|MIPS32|Add Unsigned Word
CLO|MIPS32|Count Leading Ones in Word
CLZ|MIPS32|Count Leading Zeros in Word
DIV|MIPS32|Divide Word
DIVU|MIPS32|Divide Unsigned Word
MADD|MIPS32|Multiply and Add Word to Hi, Lo
MADDU|MIPS32|Multiply and Add Unsigned Word to Hi, Lo
MSUB|MIPS32|Multiply and Subtract Word to Hi, Lo
MSUBU|MIPS32|Multiply and Subtract Unsigned Word to Hi, Lo
MUL|MIPS32|Multiply Word to GPR
MULT|MIPS32|Multiply Word
MULTU|MIPS32|Multiply Unsigned Word
SEB|MIPS32R2|Sign-Extend Byte
SEH|MIPS32R2|Sign-Extend Halftword
SLT|MIPS32|Set on Less Than
SLTI|MIPS32|Set on Less Than Immediate
SLTIU|MIPS32|Set on Less Than Immediate Unsigned
SLTU|MIPS32|Set on Less Than Unsigned
SUB|MIPS32|Subtract Word
SUBU|MIPS32|Subtract Word
//CPU Branch and Jump Instructions
B|MIPS32,AI|Unconditional Branch
BAL|MIPS32,AI|Branch and Link
BEQ|MIPS32|Branch on Equal
BGEZ|MIPS32|Branch on Greater Than or Equal to Zero
BGEZAL|MIPS32|Branch on Greater Than or Equal to Zero and Link
BGTZ|MIPS32|Branch on Greater Than Zero
BLEZ|MIPS32|Branch on Less Than or Equal to Zero
BLTZ|MIPS32|Branch on Less Than Zero
BLTZAL|MIPS32|Branch on Less Than Zero and Link
BNE|MIPS32|Branch on Not Equal
J|MIPS32|Jump
JAL|MIPS32|Jump and Link
JALR|MIPS32|Jump and Link Register
JALR.HB|MIPS32R2|Jump and Link Register with Hazard Barrier
JALX|MIPS32+MIPS16e|Jump and Link Exchange
JR|MIPS32|Jump Register
JR.HB|MIPS32R2|Jump Register with Hazard Barrier
EHB|MIPS32R2|Execution Hazard Barrier
NOP|MIPS32,AI|No Operation
PAUSE|MIPS32R2|Wait for LLBit to Clear
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
Thank you, the startup code is compiling now, I will send you a patch with the missing opcodes to have full support of mips32r2 soon. Michael Am 03.06.13 22:04, schrieb Sergei Gorelkin: 29.05.2013 21:44, Michael Ring пишет: This is looking good now on first view, all statements seem to pass through now. The only thing not working is the register error in mfc0 (and friends) command. Now I will wade through some more code to find out why my nice param -CpMIPS32R2 is ignored by assembler, it still defaults to MIPS2: I hopefully fixed this issue in r24643, and the register naming issue in r24799. Should you encounter more issues, do not hesitate to report them. Regards, Sergei ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
Sergei Gorelkin wrote: 29.05.2013 21:44, Michael Ring пишет: This is looking good now on first view, all statements seem to pass through now. The only thing not working is the register error in mfc0 (and friends) command. Now I will wade through some more code to find out why my nice param -CpMIPS32R2 is ignored by assembler, it still defaults to MIPS2: I hopefully fixed this issue in r24643, and the register naming issue in r24799. Should you encounter more issues, do not hesitate to report them. As an aside, is Fuxin Zhang (Lemote) still active in here? I've not seen anything from him here since last year but he posted to debian-mips a couple of days ago. -- Mark Morgan Lloyd markMLl .AT. telemetry.co .DOT. uk [Opinions above are the author's, not those of his employers or colleagues] ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
On 04 Jun 2013, at 10:15, Mark Morgan Lloyd wrote: As an aside, is Fuxin Zhang (Lemote) still active in here? I've not seen anything from him here since last year but he posted to debian- mips a couple of days ago. No, he unsubscribed on 23 April. Jonas ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
29.05.2013 21:44, Michael Ring пишет: This is looking good now on first view, all statements seem to pass through now. The only thing not working is the register error in mfc0 (and friends) command. Now I will wade through some more code to find out why my nice param -CpMIPS32R2 is ignored by assembler, it still defaults to MIPS2: I hopefully fixed this issue in r24643, and the register naming issue in r24799. Should you encounter more issues, do not hesitate to report them. Regards, Sergei ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
29.05.2013 2:08, Sergei Gorelkin пишет: 29.05.2013 1:26, Michael Ring пишет: I did the changes, parts of the opcodes now work fine, I think I have found the problem with the li + and + mfc0 op-codes, if last parameter is 0 then the asm statement is generated wrong: This works: and$a0,$a0,1 this does not work: and$a0,$a0,0 result is: pic32mx1xxfxxxb.s:107: Error: absolute expression required `and $a0,$a0,' So it is the value of operand that matters. I'll try to look at it, probably a bug in the parsing part, because the output part doesn't have anything suspicious. Fixed in r24630. The parsing part is buggy as hell (it interprets numbers as references rather than as constants), but the output part wasn't correct either at outputting such references. Regards, Sergei ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
Re: [fpc-devel] Some Opcodes missing in internal assembler for mips32r2
This is looking good now on first view, all statements seem to pass through now. The only thing not working is the register error in mfc0 (and friends) command. Now I will wade through some more code to find out why my nice param -CpMIPS32R2 is ignored by assembler, it still defaults to MIPS2: Target OS: Embedded Compiling pic32mx1xxfxxxb.pp Assembling pic32mx1xxfxxxb pic32mx1xxfxxxb.s: Assembler messages: pic32mx1xxfxxxb.s:37: Error: Illegal operands `mfc0 $t0,$t4,1' pic32mx1xxfxxxb.s:38: Error: Opcode not supported on this processor: mips2 (mips2) `ext $t0,$t0,19,1' pic32mx1xxfxxxb.s:49: Error: Opcode not supported on this processor: mips2 (mips2) `ext $t2,$t1,26,4' pic32mx1xxfxxxb.s:51: Error: Opcode not supported on this processor: mips2 (mips2) `ins $t1,$t2,6,4' Thank you for your help! Michael Am 29.05.13 18:13, schrieb Sergei Gorelkin: 29.05.2013 2:08, Sergei Gorelkin пишет: 29.05.2013 1:26, Michael Ring пишет: I did the changes, parts of the opcodes now work fine, I think I have found the problem with the li + and + mfc0 op-codes, if last parameter is 0 then the asm statement is generated wrong: This works: and$a0,$a0,1 this does not work: and$a0,$a0,0 result is: pic32mx1xxfxxxb.s:107: Error: absolute expression required `and $a0,$a0,' So it is the value of operand that matters. I'll try to look at it, probably a bug in the parsing part, because the output part doesn't have anything suspicious. Fixed in r24630. The parsing part is buggy as hell (it interprets numbers as references rather than as constants), but the output part wasn't correct either at outputting such references. Regards, Sergei ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
[fpc-devel] Some Opcodes missing in internal assembler for mips32r2
I am currently writing/porting startup code for the pic32 chips, the inline assembler of fpc seems to lack support for some opcodes, any idea how I can workarround this? With grep I found for example mtc1 in opcode.inc, but mtc0 is missing, this opcode is important for the initialization of the pic32 chips. Is it easy to implement those missing op-codes in the internal assembler, if yes, could some fpc-crack give me a hint on what to change where? Those are the missing opcodes: beqz ehb ext ins mfc0 mtc0 sdbbp wrpgpr Thank you in advance, Michael ___ fpc-devel maillist - fpc-devel@lists.freepascal.org http://lists.freepascal.org/mailman/listinfo/fpc-devel
