On Thu, Nov 3, 2022 at 7:52 AM Mark Millard wrote:
> On 2022-Nov-2, at 14:09, Archimedes Gaviola
> wrote:
>
> > On Mon, Oct 31, 2022 at 1:47 PM Archimedes Gaviola <
> archimedes.gavi...@gmail.com> wrote:
> >
> > . . .
> >
> > . . .
> >
> >
> > Hi Mark,
> >
> > Just an update, as kernel and world compilation is ongoing with my RPi3B
> system (with swap partition) is doing so far, so good. It already surpassed
> the tough part that breaks the compilation process here.
> > ...
> >
> > llvm-tblgen -gen-asm-matcher -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenAsmMatcher.inc.d -o RISCVGenAsmMatcher.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-asm-writer -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenAsmWriter.inc.d -o RISCVGenAsmWriter.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-callingconv -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenCallingConv.inc.d -o RISCVGenCallingConv.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-compress-inst-emitter -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenCompressInstEmitter.inc.d -o RISCVGenCompressInstEmitter.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-dag-isel -I /usr/src/contrib/llvm-project/llvm/include
> -I /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenDAGISel.inc.d -o RISCVGenDAGISel.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-disassembler -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenDisassemblerTables.inc.d -o RISCVGenDisassemblerTables.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-global-isel -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenGlobalISel.inc.d -o RISCVGenGlobalISel.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-instr-info -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenInstrInfo.inc.d -o RISCVGenInstrInfo.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-emitter -I /usr/src/contrib/llvm-project/llvm/include
> -I /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenMCCodeEmitter.inc.d -o RISCVGenMCCodeEmitter.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-pseudo-lowering -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenMCPseudoLowering.inc.d -o RISCVGenMCPseudoLowering.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-register-bank -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenRegisterBank.inc.d -o RISCVGenRegisterBank.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-register-info -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenRegisterInfo.inc.d -o RISCVGenRegisterInfo.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-searchable-tables -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenSearchableTables.inc.d -o RISCVGenSearchableTables.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-subtarget -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenSubtargetInfo.inc.d -o RISCVGenSubtargetInfo.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> > llvm-tblgen -gen-searchable-tables -I
> /usr/src/contrib/llvm-project/llvm/include -I
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV -d
> RISCVGenSystemOperands.inc.d -o RISCVGenSystemOperands.inc
> /usr/src/contrib/llvm-project/llvm/lib/Target/RISCV/RISCV.td
> >
> > Any thoughts why this part is quite a challenge when it comes to memory
> usage? The other architectures do not possess such behavior... just curious.
>
Hi Mark,
Sorry for the late response, I got fully occupied at work for the past few
days due to deliverables. Thanks for your feedback and further inputs!
> I've not done any monitoring of buildworld buildkernel build
> activity (RAM use, memory space use, swap partition use over
> time) on RPi3B class hardware in a very long time.
>
It's alright, it so happened