Per core frequency control
Hi, I was reading through cpufreq(4) and in the bugs section it mentions that per core (or CPU) frequency control is not supported. That all cores/CPUs have to be at the same speed. What is the reason for that? Is it an infrastructure problem with FreeBSD or has it just not been implemented? And how will the recent work on event timers (and a tickless kernel) impact on this problem? Regards, David signature.asc Description: This is a digitally signed message part.
Re: Per core frequency control
On 09.11.2010 11:56, David Naylor wrote: Hi, I was reading through cpufreq(4) and in the bugs section it mentions that per core (or CPU) frequency control is not supported. That all cores/CPUs have to be at the same speed. What is the reason for that? Is it an infrastructure problem with FreeBSD or has it just not been implemented? And how will the recent work on event timers (and a tickless kernel) impact on this problem? You did read the symmetric part of symmetric multi processor didn't you? It's a limitation of the technology. One clock. //Svein -- +---+--- /\ |Svein Skogen | sv...@d80.iso100.no \ / |Solberg Østli 9| PGP Key: 0xE5E76831 X|2020 Skedsmokorset | sv...@jernhuset.no / \ |Norway | PGP Key: 0xCE96CE13 | | sv...@stillbilde.net ascii | | PGP Key: 0x58CD33B6 ribbon |System Admin | svein-listm...@stillbilde.net Campaign|stillbilde.net | PGP Key: 0x22D494A4 +---+--- |msn messenger: | Mobile Phone: +47 907 03 575 |sv...@jernhuset.no | RIPE handle:SS16503-RIPE +---+--- A: Because it fouls the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail? Picture Gallery: https://gallery.stillbilde.net/v/svein/ signature.asc Description: OpenPGP digital signature
Re: Per core frequency control
On Tue, Nov 9, 2010 at 5:17 AM, Svein Skogen (Listmail account) svein-listm...@stillbilde.net wrote: You did read the symmetric part of symmetric multi processor didn't you? It's a limitation of the technology. One clock. I don't think that's quite true. The newer Intel server chipsets have the ability to throttle back idle cores and boost the speed of active ones, to improve performance on single-threaded workloads. ___ freebsd-questions@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-questions To unsubscribe, send any mail to freebsd-questions-unsubscr...@freebsd.org
Re: Per core frequency control
On Nov 9, 2010, at 9:54 AM, David Brodbeck wrote: On Tue, Nov 9, 2010 at 5:17 AM, Svein Skogen (Listmail account) svein-listm...@stillbilde.net wrote: You did read the symmetric part of symmetric multi processor didn't you? It's a limitation of the technology. One clock. I don't think that's quite true. The newer Intel server chipsets have the ability to throttle back idle cores and boost the speed of active ones, to improve performance on single-threaded workloads. You're talking about: http://en.wikipedia.org/wiki/Intel_Turbo_Boost In point of fact, what this is doing is that the CPU is adjusting it's own multipliers of Bclk (normally 133.33 MHz, although 160MHz can also used if XMP profile timing is active) if it can halt or put to sleep some of the cores into C1/C1E/C3 states. There still is only one base clock frequency being provided to all of the cores, and the ones which are still awake will still all be running at the same speed. [1] Regards, -- -Chuck [1] Modulo extreme thermal conditions involving TM1 but not TM2; TM1 thresholds are per-CPU. ___ freebsd-questions@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-questions To unsubscribe, send any mail to freebsd-questions-unsubscr...@freebsd.org
Re: Per core frequency control
On Tue, Nov 9, 2010 at 9:54 AM, David Brodbeck g...@gull.us wrote: On Tue, Nov 9, 2010 at 5:17 AM, Svein Skogen (Listmail account) svein-listm...@stillbilde.net wrote: You did read the symmetric part of symmetric multi processor didn't you? It's a limitation of the technology. One clock. I don't think that's quite true. The newer Intel server chipsets have the ability to throttle back idle cores and boost the speed of active ones, to improve performance on single-threaded workloads. AMD has similar technology on the Phenom's as well. I'm not sure how factually accurate the following link's assessment is but it's a good read either way. http://www.anandtech.com/show/3641/amd-divulges-phenom-ii-x6-secrets-turbo-core-enabled Mark ___ freebsd-questions@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/freebsd-questions To unsubscribe, send any mail to freebsd-questions-unsubscr...@freebsd.org
