[COMMITTED] RISC-V: Fix typos on comments (SVE -> RVV)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

We have the 'V' extension (RVV), not SVE from AArch64.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins.cc
(builtin_decl, expand_builtin): Replace SVE with RVV.
---
 gcc/config/riscv/riscv-vector-builtins.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
b/gcc/config/riscv/riscv-vector-builtins.cc
index 5318651138ae..5d4dc264fa61 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4172,7 +4172,7 @@ builtin_decl (unsigned int code, bool)
   return (*registered_functions)[code]->decl;
 }
 
-/* Attempt to fold STMT, given that it's a call to the SVE function
+/* Attempt to fold STMT, given that it's a call to the RVV function
with subcode CODE.  Return the new statement on success and null
on failure.  Insert any other new statements at GSI.  */
 gimple *
@@ -4192,7 +4192,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
   return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
 }
 
-/* Perform any semantic checks needed for a call to the SVE function
+/* Perform any semantic checks needed for a call to the RVV function
with subcode CODE, such as testing for integer constant expressions.
The call occurs at location LOCATION and has NARGS arguments,
given by ARGS.  FNDECL is the original function decl, before

base-commit: f45cca26263c3563e9db15e0ba64d4a114316808
-- 
2.42.0

[PATCH] RISC-V: Add builtin .def file dependencies

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

riscv-builtins.cc includes riscv-cmo.def and riscv-scalar-crypto.def
(making dependencies) but their dependencies must be explicitly defined at
the configuration file, t-riscv.

They were the last two .def files without correct dependency information.

gcc/ChangeLog:

* config/riscv/t-riscv: Add dependencies for riscv-builtins.cc,
riscv-cmo.def and riscv-scalar-crypto.def.
---
 gcc/config/riscv/t-riscv | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 104f85c6c8b1..f137e1f17ef3 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -8,7 +8,9 @@ riscv-builtins.o: $(srcdir)/config/riscv/riscv-builtins.cc 
$(CONFIG_H) \
   $(DIAGNOSTIC_CORE_H) $(OPTABS_H) $(RISCV_BUILTINS_H) \
   $(srcdir)/config/riscv/riscv-ftypes.def \
   $(srcdir)/config/riscv/riscv-vector-builtins-types.def \
-  $(srcdir)/config/riscv/riscv-modes.def
+  $(srcdir)/config/riscv/riscv-modes.def \
+  $(srcdir)/config/riscv/riscv-cmo.def \
+  $(srcdir)/config/riscv/riscv-scalar-crypto.def
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-builtins.cc
 

base-commit: 68845f7c4d58186cc0a5b09f7511f3c0a8f07e88
-- 
2.42.0

Re: [PATCH 2/2] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

[Tsukasa OI via Gcc-patches]

On 2023/09/12 11:44, Kito Cheng wrote:
> LGTM, I think llvm and GCC are inconsistent for those intrinsics API
> is really unfortunate...so really appreciate making those API align :)

I guess that you mean LGTM to this patch set (given the context).
If so, I will commit this patch set later.

> And did you have plan to add riscv_crypto.h after updating/fixing all builtin?

Like riscv_vector.h?  I don't and I think we need to discuss what to
include in... like Toolchain SIG first.

Additionally, we need to discuss what to do with these XLEN-specific
builtins specific to LLVM (my idea is, add XLEN-specific builtins like
LLVM but not to remove XLEN independent ones).

Thanks,
Tsukasa

> Excerpt from the latest clang/include/clang/Basic/BuiltinsRISCV.def:
> 
> // Zbb extension
> TARGET_BUILTIN(__builtin_riscv_orc_b_32, "UiUi", "nc", "zbb")
> TARGET_BUILTIN(__builtin_riscv_orc_b_64, "UWiUWi", "nc", "zbb,64bit")
> TARGET_BUILTIN(__builtin_riscv_clz_32, "UiUi", "nc", "zbb|xtheadbb")
> TARGET_BUILTIN(__builtin_riscv_clz_64, "UiUWi", "nc", "zbb|xtheadbb,64bit")
> TARGET_BUILTIN(__builtin_riscv_ctz_32, "UiUi", "nc", "zbb")
> TARGET_BUILTIN(__builtin_riscv_ctz_64, "UiUWi", "nc", "zbb,64bit")
> 
> // Zbc or Zbkc extension
> TARGET_BUILTIN(__builtin_riscv_clmul_32, "UiUiUi", "nc", "zbc|zbkc")
> TARGET_BUILTIN(__builtin_riscv_clmul_64, "UWiUWiUWi", "nc", "zbc|zbkc,64bit")
> TARGET_BUILTIN(__builtin_riscv_clmulh_32, "UiUiUi", "nc", "zbc|zbkc,32bit")
> TARGET_BUILTIN(__builtin_riscv_clmulh_64, "UWiUWiUWi", "nc", "zbc|zbkc,64bit")
> TARGET_BUILTIN(__builtin_riscv_clmulr_32, "UiUiUi", "nc", "zbc,32bit")
> TARGET_BUILTIN(__builtin_riscv_clmulr_64, "UWiUWiUWi", "nc", "zbc,64bit")
> 
> // Zbkx
> TARGET_BUILTIN(__builtin_riscv_xperm4_32, "UiUiUi", "nc", "zbkx,32bit")
> TARGET_BUILTIN(__builtin_riscv_xperm4_64, "UWiUWiUWi", "nc", "zbkx,64bit")
> TARGET_BUILTIN(__builtin_riscv_xperm8_32, "UiUiUi", "nc", "zbkx,32bit")
> TARGET_BUILTIN(__builtin_riscv_xperm8_64, "UWiUWiUWi", "nc", "zbkx,64bit")
> 
> // Zbkb extension
> TARGET_BUILTIN(__builtin_riscv_brev8_32, "UiUi", "nc", "zbkb")
> TARGET_BUILTIN(__builtin_riscv_brev8_64, "UWiUWi", "nc", "zbkb,64bit")
> TARGET_BUILTIN(__builtin_riscv_zip_32, "UiUi", "nc", "zbkb,32bit")
> TARGET_BUILTIN(__builtin_riscv_unzip_32, "UiUi", "nc", "zbkb,32bit")

[PATCH 1/2] RISC-V: Make bit manipulation value / round number and shift amount types for builtins unsigned

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

For bit manipulation operations, input(s) and the manipulated output are
better to be unsigned like other target-independent builtins like
__builtin_bswap32 and __builtin_popcount.

Although this is not completely compatible as before (as the type changes),
most code will run normally, even without warnings (with -Wall -Wextra).

To make consistent to the LLVM commit 599421ae36c3 ("[RISCV] Use unsigned
instead of signed types for Zk* and Zb* builtins."), round numbers and
shift amount on the scalar crypto instructions are also changed
to unsigned.

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_ATYPE_UQI): New for
uint8_t.  (RISCV_ATYPE_UHI): New for uint16_t.
(RISCV_ATYPE_QI, RISCV_ATYPE_HI, RISCV_ATYPE_SI, RISCV_ATYPE_DI):
Removed as no longer used.
(RISCV_ATYPE_UDI): New for uint64_t.
* config/riscv/riscv-cmo.def: Make types unsigned for not working
"zicbop_cbo_prefetchi" and working bit manipulation clmul builtin
argument/return types.
* config/riscv/riscv-ftypes.def: Make bit manipulation, round
number and shift amount types unsigned.
* config/riscv/riscv-scalar-crypto.def: Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbc32.c: Make signed type to unsigned.
* gcc.target/riscv/zbc64.c: Ditto.
* gcc.target/riscv/zbkb32.c: Ditto.
* gcc.target/riscv/zbkb64.c: Ditto.
* gcc.target/riscv/zbkc32.c: Ditto.
* gcc.target/riscv/zbkc64.c: Ditto.
* gcc.target/riscv/zbkx32.c: Ditto.
* gcc.target/riscv/zbkx64.c: Ditto.
* gcc.target/riscv/zknd32.c: Ditto.
* gcc.target/riscv/zknd64.c: Ditto.
* gcc.target/riscv/zkne32.c: Ditto.
* gcc.target/riscv/zkne64.c: Ditto.
* gcc.target/riscv/zknh-sha256.c: Ditto.
* gcc.target/riscv/zknh-sha512-32.c: Ditto.
* gcc.target/riscv/zknh-sha512-64.c: Ditto.
* gcc.target/riscv/zksed32.c: Ditto.
* gcc.target/riscv/zksed64.c: Ditto.
* gcc.target/riscv/zksh32.c: Ditto.
* gcc.target/riscv/zksh64.c: Ditto.
---
 gcc/config/riscv/riscv-builtins.cc|   7 +-
 gcc/config/riscv/riscv-cmo.def|  16 +--
 gcc/config/riscv/riscv-ftypes.def |  24 ++--
 gcc/config/riscv/riscv-scalar-crypto.def  | 104 +-
 gcc/testsuite/gcc.target/riscv/zbc32.c|   6 +-
 gcc/testsuite/gcc.target/riscv/zbc64.c|   6 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  10 +-
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |   8 +-
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zknd32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  10 +-
 gcc/testsuite/gcc.target/riscv/zkne32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zkne64.c   |   8 +-
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |   8 +-
 .../gcc.target/riscv/zknh-sha512-32.c |  12 +-
 .../gcc.target/riscv/zknh-sha512-64.c |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed32.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c   |   4 +-
 23 files changed, 133 insertions(+), 134 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 8afe7b7e97d3..f6b06b3c16ac 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -155,11 +155,10 @@ AVAIL (hint_pause, (!0))
 
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
+#define RISCV_ATYPE_UQI unsigned_intQI_type_node
+#define RISCV_ATYPE_UHI unsigned_intHI_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
-#define RISCV_ATYPE_QI intQI_type_node
-#define RISCV_ATYPE_HI intHI_type_node
-#define RISCV_ATYPE_SI intSI_type_node
-#define RISCV_ATYPE_DI intDI_type_node
+#define RISCV_ATYPE_UDI unsigned_intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b92044dc6ff9..ff713b78e19e 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -13,15 +13,15 @@ RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", 
RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV
 RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, zero64),
 
 // zicbop
-RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
-RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, prefetchi64),
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", 

[PATCH 2/2] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This is in parity with the LLVM commit a64b3e92c7cb ("[RISCV] Re-define
sha256, Zksed, and Zksh intrinsics to use i32 types.").

SHA-256, SM3 and SM4 instructions operate on 32-bit integers and upper
32-bits have no effects on RV64 (the output is sign-extended from the
original 32-bit value).  In that sense, making those intrinsics only
operate on uint32_t is much more natural than XLEN-bits wide integers.

This commit reforms instructions and expansions based on 32-bit
instruction handling on RV64 (such as ADDW).

Before:
   riscv__si: For RV32, fully operate on uint32_t
   riscv__di: For RV64, fully operate on uint64_t
After:
  *riscv__si: For RV32, fully operate on uint32_t
   riscv__di_extended:
  For RV64.  Input is uint32_t and output is int64_t,
  sign-extended from the int32_t result
  (represents a part of  behavior).
   riscv__si: Common (fully operate on uint32_t).
  On RV32, "expands" to *riscv__si.
  On RV64, initially expands to riscv__di_extended *and*
  extracts lower 32-bits from the int64_t result.

It also refines definitions of SHA-256, SM3 and SM4 intrinsics.

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sha256sig0_,
riscv_sha256sig1_, riscv_sha256sum0_,
riscv_sha256sum1_, riscv_sm3p0_, riscv_sm3p1_,
riscv_sm4ed_, riscv_sm4ks_): Remove and replace with
new insn/expansions.
(SHA256_OP, SM3_OP, SM4_OP): New iterators.
(sha256_op, sm3_op, sm4_op): New attributes for iteration.
(*riscv__si): New raw instruction for RV32.
(*riscv__si): Ditto.
(*riscv__si): Ditto.
(riscv__di_extended): New base instruction for RV64.
(riscv__di_extended): Ditto.
(riscv__di_extended): Ditto.
(riscv__si): New common instruction expansion.
(riscv__si): Ditto.
(riscv__si): Ditto.
* config/riscv/riscv-builtins.cc: Add availability "crypto_zknh",
"crypto_zksh" and "crypto_zksed".  Remove availability
"crypto_zksh{32,64}" and "crypto_zksed{32,64}".
* config/riscv/riscv-ftypes.def: Remove unused function type.
* config/riscv/riscv-scalar-crypto.def: Make SHA-256, SM3 and SM4
intrinsics to operate on uint32_t.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknh-sha256.c: Moved to...
* gcc.target/riscv/zknh-sha256-64.c: ...here.  Test RV64.
* gcc.target/riscv/zknh-sha256-32.c: New test for RV32.
* gcc.target/riscv/zksh64.c: Change the type.
* gcc.target/riscv/zksed64.c: Ditto.
---
 gcc/config/riscv/crypto.md| 161 --
 gcc/config/riscv/riscv-builtins.cc|   7 +-
 gcc/config/riscv/riscv-ftypes.def |   1 -
 gcc/config/riscv/riscv-scalar-crypto.def  |  24 +--
 .../gcc.target/riscv/zknh-sha256-32.c |  10 ++
 .../riscv/{zknh-sha256.c => zknh-sha256-64.c} |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c   |   4 +-
 8 files changed, 139 insertions(+), 80 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 rename gcc/testsuite/gcc.target/riscv/{zknh-sha256.c => zknh-sha256-64.c} (78%)

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index e4b7f0190dfe..03a1d03397d9 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -250,36 +250,47 @@
 
 ;; ZKNH - SHA256
 
-(define_insn "riscv_sha256sig0_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
-  UNSPEC_SHA_256_SIG0))]
-  "TARGET_ZKNH"
-  "sha256sig0\t%0,%1"
-  [(set_attr "type" "crypto")])
-
-(define_insn "riscv_sha256sig1_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
-  UNSPEC_SHA_256_SIG1))]
-  "TARGET_ZKNH"
-  "sha256sig1\t%0,%1"
+(define_int_iterator SHA256_OP [
+  UNSPEC_SHA_256_SIG0 UNSPEC_SHA_256_SIG1
+  UNSPEC_SHA_256_SUM0 UNSPEC_SHA_256_SUM1])
+(define_int_attr sha256_op [
+  (UNSPEC_SHA_256_SIG0 "sha256sig0") (UNSPEC_SHA_256_SIG1 "sha256sig1")
+  (UNSPEC_SHA_256_SUM0 "sha256sum0") (UNSPEC_SHA_256_SUM1 "sha256sum1")])
+
+(define_insn "*riscv__si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+   SHA256_OP))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "\t%0,%1"
   [(set_attr "type" "crypto")])
 
-(define_insn "riscv_sha256sum0_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
-  UNSPEC_SHA_256_SUM0))]
-  "TARGET_ZKNH"
-  "sha256sum0\t%0,%1"
+(define_insn "riscv__di_extended"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(sign_extend:DI
+ (unspec:SI [(match_operand:SI 1 

[PATCH 0/2] RISC-V: Change RISC-V bit manipulation / scalar crypto builtin types

[Tsukasa OI via Gcc-patches]

Hello,

My research suggests my previous RFC patchs will not break any real-world
programs (as far as I could find) and I will submit this patch set
(previously, two RFC patch sets) for upstream contribution.

RFC PATCH 1 (combined to this):

RFC PATCH 2 (combined to this):


This patch set consists of two commits:

1.  Changing signed types to unsigned types on bit manipulation and scalar
crypto intrinsics.
2.  Changing from uint64_t (changed from int64_t on the PATCH 1/2) to
uint32_t on SHA-256, SM3 and SM4 intrinsics (all operate on 32-bit
integers and upper 32-bits are not affected).

This is in sync with following commits in LLVM (will be a part of 17):

1. 599421ae36c3
  ("[RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.")
2. a64b3e92c7cb
  ("[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.")

Many RISC-V builtins operate in signed integer types but in many cases,
they are better to be unsigned.

It follows with a bit fixed cover letter from the previous RFC PATCH sets.

Sincerely,
Tsukasa



Many RISC-V builtins operate in signed integer types but in many cases,
they are better to be unsigned.

There are a few reasons to do that in PATCH 1/2:

1.  Being more natural
For bit manipulation operations, the direct input and the manipulated
result should have an unsigned type.
e.g. __builtin_bswap16
Both input and output should be (and are) unsigned.
e.g. __builtin_popcount
The input should be (and is) unsigned.
The output is a bit count and is in int (signed integer).
2.  In parity with LLVM (likely in version 17)
LLVM made similar changes to this patch set in the commit 599421ae36c3
("[RISCV] Use unsigned instead of signed types for Zk* and Zb*
builtins.") by Craig Topper.
Note that shift amount / round number argument types are changed to
unsigned in this LLVM commit, I did the same.
3.  Minimum compatibility breakage
This change rarely causes warnings even if both -Wall and -Wextra are
specified.

This is not completely compatible.  For instance, we will notice when
operating with for instance C++'s "auto" / "decltype" or overload
resolution.  But I consider this change in PATCH 1/2 is acceptable.



There are also operations that only operate in 32-bit integers but require
XLEN-bit wide integers.  Intrinsics for SHA-256, SM3 and SM4 applies.

PATCH 2/2 changes this in parity with the LLVM commit a64b3e92c7cb ("[RISCV]
Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.") by Craig
Topper and makes those intrinsics accept/return uint32_t even on RV64.

This instruction/expansion changes are based on the handling of 32-bit
instructions on RV64 (such as ADDW).

Before:
   riscv__si: For RV32, fully operate on uint32_t
   riscv__di: For RV64, fully operate on uint64_t
After:
  *riscv__si: For RV32, fully operate on uint32_t
   riscv__di_extended:
  For RV64. Input is uint32_t and output is int64_t,
  sign-extended from the int32_t result
  (represents a part of  behavior).
   riscv__si: Common (fully operate on uint32_t).
  On RV32, "expands" to *riscv__si.
  On RV64, initially expands to riscv__di_extended and
  extracts lower 32-bits from the int64_t result.

I think this (not completely compatible) change is still acceptable.




Tsukasa OI (2):
  RISC-V: Make bit manipulation value / round number and shift amount
types for builtins unsigned
  RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

 gcc/config/riscv/crypto.md| 161 --
 gcc/config/riscv/riscv-builtins.cc|  14 +-
 gcc/config/riscv/riscv-cmo.def|  16 +-
 gcc/config/riscv/riscv-ftypes.def |  23 ++-
 gcc/config/riscv/riscv-scalar-crypto.def  |  96 +--
 gcc/testsuite/gcc.target/riscv/zbc32.c|   6 +-
 gcc/testsuite/gcc.target/riscv/zbc64.c|   6 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  10 +-
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |   8 +-
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zknd32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  10 +-
 gcc/testsuite/gcc.target/riscv/zkne32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zkne64.c   |   8 +-
 .../gcc.target/riscv/zknh-sha256-32.c |  10 ++
 .../riscv/{zknh-sha256.c => zknh-sha256-64.c} |   8 +-
 .../gcc.target/riscv/zknh-sha512-32.c |  12 +-
 .../gcc.target/riscv/zknh-sha512-64.c |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed32.c  |  

[RFC PATCH 1/1] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This is in parity with the LLVM commit 599421ae36c3 ("[RISCV] Re-define
sha256, Zksed, and Zksh intrinsics to use i32 types.").

SHA-256, SM3 and SM4 instructions operate on 32-bit integers and upper
32-bits have no effects on RV64 (the output is sign-extended from the
original 32-bit value).  In that sense, making those intrinsics only
operate on uint32_t is much more natural than XLEN-bits wide integers.

This commit reforms instructions and expansions based on 32-bit
instruction handling on RV64 (such as ADDW).

Before:
   riscv__si: For RV32, operate on uint32_t
   riscv__di: For RV64, operate on uint64_t
After:
  *riscv__si: For RV32, operate on uint32_t
   riscv__di_extended:
  For RV64, input is uint32_t and...
  output is sign-extended int64_t.
   riscv__si: Common and expands to either of above.
  On RV64, extract lower 32-bits from the int64_t result.

It also refines definitions of SHA-256, SM3 and SM4 intrinsics.

gcc/ChangeLog:

* config/riscv/crypto.md (riscv_sha256sig0_,
riscv_sha256sig1_, riscv_sha256sum0_,
riscv_sha256sum1_, riscv_sm3p0_, riscv_sm3p1_,
riscv_sm4ed_, riscv_sm4ks_): Remove and replace with
new insn/expansions.
(SHA256_OP, SM3_OP, SM4_OP): New iterators.
(sha256_op, sm3_op, sm4_op): New attributes for iteration.
(*riscv__si): New raw instruction for RV32.
(*riscv__si): Ditto.
(*riscv__si): Ditto.
(riscv__di_extended): New base instruction for RV64.
(riscv__di_extended): Ditto.
(riscv__di_extended): Ditto.
(riscv__si): New common instruction expansion.
(riscv__si): Ditto.
(riscv__si): Ditto.
* config/riscv/riscv-builtins.cc: Add availability "crypto_zknh",
"crypto_zksh" and "crypto_zksed".  Remove availability
"crypto_zksh{32,64}" and "crypto_zksed{32,64}".
* config/riscv/riscv-ftypes.def: Remove unused function type.
* config/riscv/riscv-scalar-crypto.def: Make SHA-256, SM3 and SM4
intrinsics to operate on uint32_t.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zknh-sha256.c: Moved to...
* gcc.target/riscv/zknh-sha256-64.c: ...here.  Test RV64.
* gcc.target/riscv/zknh-sha256-32.c: New test for RV32.
* gcc.target/riscv/zksh64.c: Change the type.
* gcc.target/riscv/zksed64.c: Ditto.
---
 gcc/config/riscv/crypto.md| 161 --
 gcc/config/riscv/riscv-builtins.cc|   7 +-
 gcc/config/riscv/riscv-ftypes.def |   1 -
 gcc/config/riscv/riscv-scalar-crypto.def  |  24 +--
 .../gcc.target/riscv/zknh-sha256-32.c |  10 ++
 .../riscv/{zknh-sha256.c => zknh-sha256-64.c} |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c   |   4 +-
 8 files changed, 139 insertions(+), 80 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 rename gcc/testsuite/gcc.target/riscv/{zknh-sha256.c => zknh-sha256-64.c} (78%)

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index e4b7f0190dfe..03a1d03397d9 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -250,36 +250,47 @@
 
 ;; ZKNH - SHA256
 
-(define_insn "riscv_sha256sig0_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
-  UNSPEC_SHA_256_SIG0))]
-  "TARGET_ZKNH"
-  "sha256sig0\t%0,%1"
-  [(set_attr "type" "crypto")])
-
-(define_insn "riscv_sha256sig1_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
-  UNSPEC_SHA_256_SIG1))]
-  "TARGET_ZKNH"
-  "sha256sig1\t%0,%1"
+(define_int_iterator SHA256_OP [
+  UNSPEC_SHA_256_SIG0 UNSPEC_SHA_256_SIG1
+  UNSPEC_SHA_256_SUM0 UNSPEC_SHA_256_SUM1])
+(define_int_attr sha256_op [
+  (UNSPEC_SHA_256_SIG0 "sha256sig0") (UNSPEC_SHA_256_SIG1 "sha256sig1")
+  (UNSPEC_SHA_256_SUM0 "sha256sum0") (UNSPEC_SHA_256_SUM1 "sha256sum1")])
+
+(define_insn "*riscv__si"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+   SHA256_OP))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "\t%0,%1"
   [(set_attr "type" "crypto")])
 
-(define_insn "riscv_sha256sum0_"
-  [(set (match_operand:X 0 "register_operand" "=r")
-(unspec:X [(match_operand:X 1 "register_operand" "r")]
-  UNSPEC_SHA_256_SUM0))]
-  "TARGET_ZKNH"
-  "sha256sum0\t%0,%1"
+(define_insn "riscv__di_extended"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+(sign_extend:DI
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+SHA256_OP)))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "\t%0,%1"
   [(set_attr "type" "crypto")])
 
-(define_insn "riscv_sha256sum1_"
-  [(set (match_operand:X 0 

[RFC PATCH 0/1] RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

[Tsukasa OI via Gcc-patches]

Hi,

This is built on another RFC PATCH "RISC-V: Change RISC-V bit manipulation
/ scalar crypto builtin types" and changes SHA-256, SM3 and SM4 intrinsics
operate on uint32_t, not on XLEN-bit wide integers.

This is in parity with the LLVM commit 599421ae36c3 ("[RISCV] Re-define
sha256, Zksed, and Zksh intrinsics to use i32 types.") by Craig Topper.

Because we had to refine the base instruction definitions, it was way harder
than that of LLVM.  Thankfully, we have a similar example: 32-bit integer
instructions on RV64 such as ADDW.

Before:
   riscv__si: For RV32, fully operate on uint32_t
   riscv__di: For RV64, fully operate on uint64_t
After:
  *riscv__si: For RV32, fully operate on uint32_t
   riscv__di_extended:
  For RV64, input is uint32_t and output is int64_t,
  sign-extended from the int32_t result
  (represents a part of  behavior).
   riscv__si: Common (fully operate on uint32_t).
  On RV32, expands to *riscv__si.
  On RV64, initially expands to riscv__di_extended *and*
  extracts lower 32-bits from the int64_t result.

Sincerely,
Tsukasa




Tsukasa OI (1):
  RISC-V: Make SHA-256, SM3 and SM4 builtins operate on uint32_t

 gcc/config/riscv/crypto.md| 161 --
 gcc/config/riscv/riscv-builtins.cc|   7 +-
 gcc/config/riscv/riscv-ftypes.def |   1 -
 gcc/config/riscv/riscv-scalar-crypto.def  |  24 +--
 .../gcc.target/riscv/zknh-sha256-32.c |  10 ++
 .../riscv/{zknh-sha256.c => zknh-sha256-64.c} |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c   |   4 +-
 8 files changed, 139 insertions(+), 80 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256-32.c
 rename gcc/testsuite/gcc.target/riscv/{zknh-sha256.c => zknh-sha256-64.c} (78%)


base-commit: daaed758517c81fc8f8bc6502be648aca51ab278
prerequisite-patch-id: 4f4a84ebc0c33ea159db4dcd70fa8894f27c638a
prerequisite-patch-id: d2b85f777b042d349c5e232979ee219c8147c154
-- 
2.42.0

[RFC PATCH 2/2] RISC-V: Update testsuite for type-changed builtins

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This commit replaces the type of the builtin used in the testsuite.

Even without this commit, it won't cause any test failures but changed so
that no confusion occurs.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbc32.c: Make signed type to unsigned.
* gcc.target/riscv/zbc64.c: Ditto.
* gcc.target/riscv/zbkb32.c: Ditto.
* gcc.target/riscv/zbkb64.c: Ditto.
* gcc.target/riscv/zbkc32.c: Ditto.
* gcc.target/riscv/zbkc64.c: Ditto.
* gcc.target/riscv/zbkx32.c: Ditto.
* gcc.target/riscv/zbkx64.c: Ditto.
* gcc.target/riscv/zknd32.c: Ditto.
* gcc.target/riscv/zknd64.c: Ditto.
* gcc.target/riscv/zkne32.c: Ditto.
* gcc.target/riscv/zkne64.c: Ditto.
* gcc.target/riscv/zknh-sha256.c: Ditto.
* gcc.target/riscv/zknh-sha512-32.c: Ditto.
* gcc.target/riscv/zknh-sha512-64.c: Ditto.
* gcc.target/riscv/zksed32.c: Ditto.
* gcc.target/riscv/zksed64.c: Ditto.
* gcc.target/riscv/zksh32.c: Ditto.
* gcc.target/riscv/zksh64.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/zbc32.c  |  6 +++---
 gcc/testsuite/gcc.target/riscv/zbc64.c  |  6 +++---
 gcc/testsuite/gcc.target/riscv/zbkb32.c | 10 +-
 gcc/testsuite/gcc.target/riscv/zbkb64.c |  8 
 gcc/testsuite/gcc.target/riscv/zbkc32.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zbkc64.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zbkx32.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zbkx64.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zknd32.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zknd64.c | 10 +-
 gcc/testsuite/gcc.target/riscv/zkne32.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zkne64.c |  8 
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c|  8 
 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c | 12 ++--
 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c |  8 
 gcc/testsuite/gcc.target/riscv/zksed32.c|  4 ++--
 gcc/testsuite/gcc.target/riscv/zksed64.c|  4 ++--
 gcc/testsuite/gcc.target/riscv/zksh32.c |  4 ++--
 gcc/testsuite/gcc.target/riscv/zksh64.c |  4 ++--
 19 files changed, 58 insertions(+), 58 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/zbc32.c 
b/gcc/testsuite/gcc.target/riscv/zbc32.c
index 08705c4a687e..f3fb2238f7f4 100644
--- a/gcc/testsuite/gcc.target/riscv/zbc32.c
+++ b/gcc/testsuite/gcc.target/riscv/zbc32.c
@@ -3,17 +3,17 @@
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 #include 
 
-int32_t foo1(int32_t rs1, int32_t rs2)
+uint32_t foo1(uint32_t rs1, uint32_t rs2)
 {
 return __builtin_riscv_clmul(rs1, rs2);
 }
 
-int32_t foo2(int32_t rs1, int32_t rs2)
+uint32_t foo2(uint32_t rs1, uint32_t rs2)
 {
 return __builtin_riscv_clmulh(rs1, rs2);
 }
 
-int32_t foo3(int32_t rs1, int32_t rs2)
+uint32_t foo3(uint32_t rs1, uint32_t rs2)
 {
 return __builtin_riscv_clmulr(rs1, rs2);
 }
diff --git a/gcc/testsuite/gcc.target/riscv/zbc64.c 
b/gcc/testsuite/gcc.target/riscv/zbc64.c
index a19f42b2883f..841a0aa7847d 100644
--- a/gcc/testsuite/gcc.target/riscv/zbc64.c
+++ b/gcc/testsuite/gcc.target/riscv/zbc64.c
@@ -3,17 +3,17 @@
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 #include 
 
-int64_t foo1(int64_t rs1, int64_t rs2)
+uint64_t foo1(uint64_t rs1, uint64_t rs2)
 {
 return __builtin_riscv_clmul(rs1, rs2);
 }
 
-int64_t foo2(int64_t rs1, int64_t rs2)
+uint64_t foo2(uint64_t rs1, uint64_t rs2)
 {
 return __builtin_riscv_clmulh(rs1, rs2);
 }
 
-int64_t foo3(int64_t rs1, int64_t rs2)
+uint64_t foo3(uint64_t rs1, uint64_t rs2)
 {
 return __builtin_riscv_clmulr(rs1, rs2);
 }
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c 
b/gcc/testsuite/gcc.target/riscv/zbkb32.c
index dd45b8b9dc72..b2e442dc49d8 100644
--- a/gcc/testsuite/gcc.target/riscv/zbkb32.c
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -4,27 +4,27 @@
 
 #include 
 
-int32_t foo1(int16_t rs1, int16_t rs2)
+uint32_t foo1(uint16_t rs1, uint16_t rs2)
 {
 return __builtin_riscv_pack(rs1, rs2);
 }
 
-int32_t foo2(int8_t rs1, int8_t rs2)
+uint32_t foo2(uint8_t rs1, uint8_t rs2)
 {
 return __builtin_riscv_packh(rs1, rs2);
 }
 
-int32_t foo3(int32_t rs1)
+uint32_t foo3(uint32_t rs1)
 {
 return __builtin_riscv_brev8(rs1);
 }
 
-int32_t foo4(int32_t rs1)
+uint32_t foo4(uint32_t rs1)
 {
 return __builtin_riscv_zip(rs1);
 }
 
-int32_t foo5(int32_t rs1)
+uint32_t foo5(uint32_t rs1)
 {
 return __builtin_riscv_unzip(rs1);
 }
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c 
b/gcc/testsuite/gcc.target/riscv/zbkb64.c
index 960a2ae30ed6..08ac9c2a9f00 100644
--- a/gcc/testsuite/gcc.target/riscv/zbkb64.c
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -3,22 +3,22 @@
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 #include 
 
-int64_t foo1(int32_t rs1, int32_t rs2)
+uint64_t foo1(uint32_t rs1, uint32_t rs2)
 {
 return 

[RFC PATCH 1/2] RISC-V: Make bit manipulation value / round number and shift amount types for builtins unsigned

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

For bit manipulation operations, inputs and the manipulated output are
better to be unsigned like other target-independent builtins like
__builtin_bswap32 and __builtin_popcount.

Although this is not completely compatible as before (as the type changes),
most code will run normally, even without warnings (with -Wall -Wextra).

Round numbers and shift amount on the scalar crypto instructions are
changed to unsigned in parity with LLVM 17 commit 599421ae36c3
("[RISCV] Use unsigned instead of signed types for Zk* and Zb* builtins.").

gcc/ChangeLog:

* config/riscv/riscv-builtins.cc (RISCV_ATYPE_UQI): New for
uint8_t.  (RISCV_ATYPE_UHI): New for uint16_t.
(RISCV_ATYPE_QI, RISCV_ATYPE_HI, RISCV_ATYPE_SI, RISCV_ATYPE_DI):
Removed as no longer used.
(RISCV_ATYPE_UDI): New for uint64_t.
* config/riscv/riscv-cmo.def: Make types unsigned for not working
"zicbop_cbo_prefetchi" and working bit manipulation clmul builtin
argument/return types.
* config/riscv/riscv-ftypes.def: Make bit manipulation, round
number and shift amount types unsigned.
* config/riscv/riscv-scalar-crypto.def: Ditto.
---
 gcc/config/riscv/riscv-builtins.cc   |   7 +-
 gcc/config/riscv/riscv-cmo.def   |  16 ++--
 gcc/config/riscv/riscv-ftypes.def|  24 +++---
 gcc/config/riscv/riscv-scalar-crypto.def | 104 +++
 4 files changed, 75 insertions(+), 76 deletions(-)

diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 8afe7b7e97d3..f6b06b3c16ac 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -155,11 +155,10 @@ AVAIL (hint_pause, (!0))
 
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
+#define RISCV_ATYPE_UQI unsigned_intQI_type_node
+#define RISCV_ATYPE_UHI unsigned_intHI_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
-#define RISCV_ATYPE_QI intQI_type_node
-#define RISCV_ATYPE_HI intHI_type_node
-#define RISCV_ATYPE_SI intSI_type_node
-#define RISCV_ATYPE_DI intDI_type_node
+#define RISCV_ATYPE_UDI unsigned_intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
 
 /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists
diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b92044dc6ff9..ff713b78e19e 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -13,15 +13,15 @@ RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", 
RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV
 RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, zero64),
 
 // zicbop
-RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
-RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, prefetchi64),
+RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI, prefetchi32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_UDI_FTYPE_UDI, prefetchi64),
 
 // zbkc or zbc
-RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, 
clmul_zbkc32_or_zbc32),
-RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, 
clmul_zbkc64_or_zbc64),
-RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI, clmul_zbkc32_or_zbc32),
-RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI_DI, clmul_zbkc64_or_zbc64),
+RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
+RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, 
RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
+RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI, clmul_zbkc32_or_zbc32),
+RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, 
RISCV_UDI_FTYPE_UDI_UDI, clmul_zbkc64_or_zbc64),
 
 // zbc
-RISCV_BUILTIN (clmulr_si, "clmulr", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI_SI, clmulr_zbc32),
-RISCV_BUILTIN (clmulr_di, "clmulr", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI_DI, clmulr_zbc64),
+RISCV_BUILTIN (clmulr_si, "clmulr", RISCV_BUILTIN_DIRECT, 
RISCV_USI_FTYPE_USI_USI, clmulr_zbc32),
+RISCV_BUILTIN (clmulr_di, "clmulr", RISCV_BUILTIN_DIRECT, 
RISCV_UDI_FTYPE_UDI_UDI, clmulr_zbc64),
diff --git a/gcc/config/riscv/riscv-ftypes.def 
b/gcc/config/riscv/riscv-ftypes.def
index 3b518195a29c..366861ce640e 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -30,15 +30,15 @@ DEF_RISCV_FTYPE (0, (USI))
 DEF_RISCV_FTYPE (0, (VOID))
 DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
-DEF_RISCV_FTYPE (1, (SI, SI))
-DEF_RISCV_FTYPE (1, (DI, DI))
-DEF_RISCV_FTYPE (2, (SI, QI, QI))
-DEF_RISCV_FTYPE (2, (SI, HI, HI))
-DEF_RISCV_FTYPE (2, (SI, SI, SI))
-DEF_RISCV_FTYPE (2, (DI, QI, QI))
-DEF_RISCV_FTYPE 

[RFC PATCH 0/2] RISC-V: Change RISC-V bit manipulation / scalar crypto builtin types

[Tsukasa OI via Gcc-patches]

Hello,

Many RISC-V builtins operate in signed integer types but in many cases,
they are better to be unsigned.

There are a few reasons to do that:

1.  Being more natural
For bit manipulation operations, the direct input and the result should
have an unsigned type.
e.g. __builtin_bswap16
Both input and output should be (and are) unsigned.
e.g. __builtin_popcount
The input should be (and is) unsigned.
The output is a bit count and is in int (signed integer).
2.  In parity with LLVM 17
LLVM made similar changes to this patch set in commit 599421ae36c3
("[RISCV] Use unsigned instead of signed types for Zk* and Zb*
builtins.") by Craig Topper.
Note that shift amount / round number argument types are changed to
unsigned in this LLVM commit, I did the same.
3.  Minimum compatibility breakage
This change rarely causes warnings even if both -Wall and -Wextra are
specified.  In fact, only applying PATCH 1/2 does not cause any
additional test failures.  PATCH 2/2 only contains testsuite changes
(uses correct types as the builtin uses).

But not completely compatible.  For instance, we will notice when operating
with for instance C++'s "auto" / "decltype" or overload resolution.

So, I would like to hear your thoughts first.

Note that, the only reason I separated this RFC patch set to two patches
is to demonstrate that no additional warnings occur even if only PATCH 1/2
is applied.  If approved or leaves an RFC PATCH, both will be merged.


p.s.

LLVM has another type of different builtin types (with the same name),
scalar cryptography builtins that operate in 32-bit integers, not XLEN-
specific (applies to SHA-256, SM3 and SM4).  For those cases, GCC prefers
XLEN-specific integer type but LLVM 17 always prefers uint32_t.

This is a result of LLVM commit 599421ae36c3 ("[RISCV] Re-define sha256,
Zksed, and Zksh intrinsics to use i32 types.").

Because just changing the width causes errors on GCC, even if I change them
to uint32_t, that would be in a different patch set.


Sincerely,
Tsukasa




Tsukasa OI (2):
  RISC-V: Make bit manipulation value / round number and shift amount
types for builtins unsigned
  RISC-V: Update testsuite for type-changed builtins

 gcc/config/riscv/riscv-builtins.cc|   7 +-
 gcc/config/riscv/riscv-cmo.def|  16 +--
 gcc/config/riscv/riscv-ftypes.def |  24 ++--
 gcc/config/riscv/riscv-scalar-crypto.def  | 104 +-
 gcc/testsuite/gcc.target/riscv/zbc32.c|   6 +-
 gcc/testsuite/gcc.target/riscv/zbc64.c|   6 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c   |  10 +-
 gcc/testsuite/gcc.target/riscv/zbkb64.c   |   8 +-
 gcc/testsuite/gcc.target/riscv/zbkc32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkc64.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkx32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkx64.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zknd32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zknd64.c   |  10 +-
 gcc/testsuite/gcc.target/riscv/zkne32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zkne64.c   |   8 +-
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |   8 +-
 .../gcc.target/riscv/zknh-sha512-32.c |  12 +-
 .../gcc.target/riscv/zknh-sha512-64.c |   8 +-
 gcc/testsuite/gcc.target/riscv/zksed32.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksed64.c  |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh32.c   |   4 +-
 gcc/testsuite/gcc.target/riscv/zksh64.c   |   4 +-
 23 files changed, 133 insertions(+), 134 deletions(-)


base-commit: af88776caa20342482b11ccb580742a46c621250
-- 
2.42.0

Re: [PATCH v3] RISC-V:Optimize the MASK opt generation

[Tsukasa OI via Gcc-patches]

Hi,

I will need to notify you that x_riscv_xventana_subext,
MASK_XVENTANACONDOPS and TARGET_XVENTANACONDOPS are added (I think you
want to rewrite those definitions like the rest).  Also, be careful not
to remove TARGET_ZICOND_LIKE.

Thanks,
Tsukasa

On 2023/09/06 11:02, Feng Wang wrote:
> This patch rebases the change of "[PATCH] RISC-V: Optimize the MASK opt
> generation" and add the new explanation in the options.texi.
> Please check the detail info on the
> "https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg302295.html;
> gcc/ChangeLog:
> 
> * config/riscv/riscv-opts.h (MASK_ZICSR):
> (MASK_ZIFENCEI): Delete;
> (MASK_ZIHINTNTL):Ditto;
> (MASK_ZIHINTPAUSE):  Ditto;
> (TARGET_ZICSR):  Ditto;
> (TARGET_ZIFENCEI):   Ditto;
> (TARGET_ZIHINTNTL):  Ditto;
> (TARGET_ZIHINTPAUSE):Ditto;
> (MASK_ZAWRS):Ditto;
> (TARGET_ZAWRS):  Ditto;
> (MASK_ZBA):  Ditto;
> (MASK_ZBB):  Ditto;
> (MASK_ZBC):  Ditto;
> (MASK_ZBS):  Ditto;
> (TARGET_ZBA):Ditto;
> (TARGET_ZBB):Ditto;
> (TARGET_ZBC):Ditto;
> (TARGET_ZBS):Ditto;
> (MASK_ZFINX):Ditto;
> (MASK_ZDINX):Ditto;
> (MASK_ZHINX):Ditto;
> (MASK_ZHINXMIN): Ditto;
> (TARGET_ZFINX):  Ditto;
> (TARGET_ZDINX):  Ditto;
> (TARGET_ZHINX):  Ditto;
> (TARGET_ZHINXMIN):   Ditto;
> (MASK_ZBKB): Ditto;
> (MASK_ZBKC): Ditto;
> (MASK_ZBKX): Ditto;
> (MASK_ZKNE): Ditto;
> (MASK_ZKND): Ditto;
> (MASK_ZKNH): Ditto;
> (MASK_ZKR):  Ditto;
> (MASK_ZKSED):Ditto;
> (MASK_ZKSH): Ditto;
> (MASK_ZKT):  Ditto;
> (TARGET_ZBKB):   Ditto;
> (TARGET_ZBKC):   Ditto;
> (TARGET_ZBKX):   Ditto;
> (TARGET_ZKNE):   Ditto;
> (TARGET_ZKND):   Ditto;
> (TARGET_ZKNH):   Ditto;
> (TARGET_ZKR):Ditto;
> (TARGET_ZKSED):  Ditto;
> (TARGET_ZKSH):   Ditto;
> (TARGET_ZKT):Ditto;
> (MASK_ZTSO): Ditto;
> (TARGET_ZTSO):   Ditto;
> (MASK_VECTOR_ELEN_32):   Ditto;
> (MASK_VECTOR_ELEN_64):   Ditto;
> (MASK_VECTOR_ELEN_FP_32):Ditto;
> (MASK_VECTOR_ELEN_FP_64):Ditto;
> (MASK_VECTOR_ELEN_FP_16):Ditto;
> (TARGET_VECTOR_ELEN_32): Ditto;
> (TARGET_VECTOR_ELEN_64): Ditto;
> (TARGET_VECTOR_ELEN_FP_32):Ditto;
> (TARGET_VECTOR_ELEN_FP_64):Ditto;
> (TARGET_VECTOR_ELEN_FP_16):Ditto;
>  (MASK_ZVBB):   Ditto;
> (MASK_ZVBC):   Ditto;
> (TARGET_ZVBB): Ditto;
> (TARGET_ZVBC): Ditto;
> (MASK_ZVKG):   Ditto;
> (MASK_ZVKNED): Ditto;
> (MASK_ZVKNHA): Ditto;
> (MASK_ZVKNHB): Ditto;
> (MASK_ZVKSED): Ditto;
> (MASK_ZVKSH):  Ditto;
> (MASK_ZVKN):   Ditto;
> (MASK_ZVKNC):  Ditto;
> (MASK_ZVKNG):  Ditto;
> (MASK_ZVKS):   Ditto;
> (MASK_ZVKSC):  Ditto;
> (MASK_ZVKSG):  Ditto;
> (MASK_ZVKT):   Ditto;
> (TARGET_ZVKG): Ditto;
> (TARGET_ZVKNED):   Ditto;
> (TARGET_ZVKNHA):   Ditto;
> (TARGET_ZVKNHB):   Ditto;
> (TARGET_ZVKSED):   Ditto;
> (TARGET_ZVKSH):Ditto;
> (TARGET_ZVKN): Ditto;
> (TARGET_ZVKNC):Ditto;
> (TARGET_ZVKNG):Ditto;
> (TARGET_ZVKS): Ditto;
> (TARGET_ZVKSC):Ditto;
> (TARGET_ZVKSG):Ditto;
> (TARGET_ZVKT): Ditto;
> (MASK_ZVL32B): Ditto;
> (MASK_ZVL64B): Ditto;
> (MASK_ZVL128B):Ditto;
> (MASK_ZVL256B):Ditto;
> (MASK_ZVL512B):Ditto;
> (MASK_ZVL1024B):   Ditto;
> (MASK_ZVL2048B):   Ditto;
> (MASK_ZVL4096B):   Ditto;
> (MASK_ZVL8192B):   Ditto;
> (MASK_ZVL16384B):  Ditto;
> (MASK_ZVL32768B):  Ditto;
> (MASK_ZVL65536B):  Ditto;
> (TARGET_ZVL32B):   Ditto;
> (TARGET_ZVL64B):   Ditto;
> (TARGET_ZVL128B):  Ditto;
> (TARGET_ZVL256B):  Ditto;
> (TARGET_ZVL512B):  Ditto;
> (TARGET_ZVL1024B): Ditto;
> (TARGET_ZVL2048B): Ditto;
> (TARGET_ZVL4096B): Ditto;
> (TARGET_ZVL8192B): Ditto;
> (TARGET_ZVL16384B):Ditto;
> (TARGET_ZVL32768B):Ditto;
> (TARGET_ZVL65536B):Ditto;
> 

Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions

[Tsukasa OI via Gcc-patches]

On 2023/09/07 2:50, Edwin Lu wrote:
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
> 
> gcc/ChangeLog:
> 
>   * config/riscv/riscv.md: Add "zicond" type
>   * config/riscv/zicond.md: Update types
> 
> Signed-off-by: Edwin Lu 
> ---
>  gcc/config/riscv/riscv.md  | 5 +++--
>  gcc/config/riscv/zicond.md | 8 
>  2 files changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6684ad89cff..c329f55db43 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
>  ;; cbocache block instructions
>  ;; crypto cryptography instructions
>  ;; csrcode size reduction instructions
> +;; zicondzicond instructions
>  ;; Classification of RVV instructions which will be added to each RVV .md 
> pattern and used by scheduler.
>  ;; rdvlenb vector byte length vlenb csrr read
>  ;; rdvlvector length vl csrr read
> @@ -422,8 +423,8 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> -   atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> -   vlde,vste,vldm,vstm,vlds,vsts,
> +   atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
> +   vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
> 
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
> diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
> index 1721e1011ea..0269bd14399 100644
> --- a/gcc/config/riscv/zicond.md
> +++ b/gcc/config/riscv/zicond.md
> @@ -30,7 +30,7 @@ (define_insn "*czero.."
>(const_int 0)))]
>"TARGET_ZICOND"
>"czero.\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>  
>  (define_insn "*czero.."
>[(set (match_operand:GPR 0 "register_operand" "=r")
> @@ -40,7 +40,7 @@ (define_insn "*czero.."
>(match_operand:GPR 2 "register_operand"   "r")))]
>"TARGET_ZICOND"
>"czero.\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>  
>  ;; Special optimization under eq/ne in primitive semantics
>  (define_insn "*czero.eqz..opt1"
> @@ -51,7 +51,7 @@ (define_insn "*czero.eqz..opt1"
>(match_operand:GPR 3 "register_operand" "r")))]
>"TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
>"czero.eqz\t%0,%3,%1"
> -)
> +[(set_attr "type" "zicond")])
>  
>  (define_insn "*czero.nez..opt2"
>[(set (match_operand:GPR 0 "register_operand"   "=r")
> @@ -61,7 +61,7 @@ (define_insn "*czero.nez..opt2"
>(match_operand:GPR 3 "register_operand" "1")))]
>"TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
>"czero.eqz\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>  
>  ;; Combine creates this form in some cases (particularly the coremark
>  ;; CRC loop.

Looks okay to me but will need to resolve merge conflicts after commit
af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
'Zicond' support").

Thanks,
Tsukasa

[PATCH v4 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.

And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).

*   czero.eqz == vt.maskc
*   czero.nez == vt.maskcn

This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support.  With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.

The specification for the 'XVentanaCondOps' extension is based on:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'.  It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero..): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero..): Ditto.
(*czero.eqz..opt1): Ditto.
(*czero.nez..opt2): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test,
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 53 +++
 .../xventanacondops-primitiveSemantics-rv32.c |  8 +++
 .../xventanacondops-primitiveSemantics.c  | 10 
 .../gcc.target/riscv/xventanacondops-xor-01.c |  8 +++
 9 files changed, 82 insertions(+), 14 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
 
+  {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index b6b5907e111b..a525f679683c 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -321,6 +321,12 @@ enum riscv_entity
 #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
 #define TARGET_XTHEADSYNC((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
 
+#define MASK_XVENTANACONDOPS  (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) 
!= 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && 
TARGET_64BIT))
+
 /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes.  */
 #define TARGET_VECTOR_VLS  
\
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 475fb2841427..a6e58e4f1159 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2744,7 +2744,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  *total = COSTS_N_INSNS (1);
  return true;
}
-  else if (TARGET_ZICOND
+  else if (TARGET_ZICOND_LIKE
   && outer_code == SET
   && ((GET_CODE (XEXP (x, 1)) == REG
&& XEXP (x, 

[PATCH v4 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

PATCH v1:

PATCH v2:

PATCH v3:


Changes: v1 -> v2
*   Removed bogus opt2 pattern as pointed out in:

note that this is not in the ChangeLog expecting the patch above
applies first.

Changes: v2 -> v3
*   Instead of removing opt2 pattern, fix opt2 pattern:


Changes: v3 -> v4
*   Leave only specific condition on {eq,ne}z_ventana code_attr.
(eqz_ventana, nez_ventana): "maskcn" -> "n", "maskc" -> ""
(*czero..) "vt." -> "vt.maskc"
(*czero..) "vt." -> "vt.maskc"
*   Testsuite:
Reuse "zicond-*.c" (#include from "xventanacondops-*.c")
*   Minor Comment: ";; Zicond" -> ";; Zicond / XVentanaCondOps"
*   Rebase against commit e87212ead5e9 ("RISC-V: zicond: Fix opt2 pattern")


On 2023/09/06 12:07, Jeff Law wrote:
> You actually don't even have to break out the common parts.  The dg-
> directives in an included file aren't parsed by the dg framework.

Wow, that was right.  It can be sometimes confusing but very useful
in this case.  Thanks for the info!


Sincerely,
Tsukasa




Tsukasa OI (1):
  RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 53 +++
 .../xventanacondops-primitiveSemantics-rv32.c |  8 +++
 .../xventanacondops-primitiveSemantics.c  | 10 
 .../gcc.target/riscv/xventanacondops-xor-01.c |  8 +++
 9 files changed, 82 insertions(+), 14 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c


base-commit: c1597e7fb9f9ecb9d7c33b5afa48031f284375de
-- 
2.42.0

[COMMITTED] RISC-V: typo: add closing paren to a comment

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

gcc/ChangeLog:

* config/riscv/zicond.md: Add closing parent to a comment.
---
 gcc/config/riscv/zicond.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 1721e1011ea8..c28bee5d5709 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -64,7 +64,7 @@
 )
 
 ;; Combine creates this form in some cases (particularly the coremark
-;; CRC loop.
+;; CRC loop).
 (define_split
   [(set (match_operand:X 0 "register_operand")
(and:X (sign_extract:X (match_operand:X 1 "register_operand")

base-commit: ce65641354d98fc80912d5516b7fea87c344c2cc
-- 
2.42.0

Re: [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

On 2023/09/06 9:17, Jeff Law wrote:
> 
> 
> On 9/5/23 06:10, Tsukasa OI wrote:
>> From: Tsukasa OI 
>>
>> 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
>> containing two instructions for conditional move and will be supported on
>> their Veyron V1 CPU.
>>
>> And most notably (for historical reasons), 'XVentanaCondOps' and the
>> standard 'Zicond' extension are functionally equivalent (only
>> encodings and
>> instruction names are different).
>>
>> *   czero.eqz == vt.maskc
>> *   czero.nez == vt.maskcn
>>
>> This commit adds support for the 'XVentanaCondOps' extension by extending
>> 'Zicond' extension support.  With this, we can now reuse the optimization
>> using the 'Zicond' extension for the 'XVentanaCondOps' extension.
>>
>> The specification for the 'XVentanaCondOps' extension is based on:
>> 
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
>> Parse 'XVentanaCondOps' extension.
>> * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
>> (TARGET_XVENTANACONDOPS): Ditto.
>> (TARGET_ZICOND_LIKE): New to represent targets with conditional
>> moves like 'Zicond'.  It includes RV64 + 'XVentanaCondOps'.
>> * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
>> with TARGET_ZICOND_LIKE.
>> (riscv_expand_conditional_move): Ditto.
>> * config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with
>> TARGET_ZICOND_LIKE.
>> * config/riscv/riscv.opt: Add new riscv_xventana_subext.
>> * config/riscv/zicond.md: Modify description.
>> (eqz_ventana): New to match corresponding czero instructions.
>> (nez_ventana): Ditto.
>> (*czero..): Emit a 'XVentanaCondOps' instruction if
>> 'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
>> (*czero..): Ditto.
>> (*czero.eqz..opt1): Ditto.
>> (*czero.nez..opt2): Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
>> modified from zicond-primitiveSemantics.c.
>> * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
>> test to make sure that XVentanaCondOps instructions are disabled
>> on RV32.
>> * gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
>> from zicond-xor-01.c.
>> ---
>>   gcc/common/config/riscv/riscv-common.cc   |  2 +
>   \
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 8d8f7b4f16ed..eb10f4a3323f 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -2745,7 +2745,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
>> outer_code, int opno ATTRIBUTE_UN
>>     *total = COSTS_N_INSNS (1);
>>     return true;
>>   }
>> -  else if (TARGET_ZICOND
>> +  else if (TARGET_ZICOND_LIKE
> Internally we have this as:
> 
> (TARGET_ZICOND || TARGET_XVENTANACONDOPS)
> 
> I don't really care, so I'm happy to go with yours.

Because XVentanaCondOps instructions are only available on 64-bit target
(I wanted to prevent misuses because we don't reject XVentanaCondOps on
RV32), the target expression would be:

(a) (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))

and I had three options to deal with it.

1.  Use the plain expression (a)
2.  Name the expression (a)
3.  Enable TARGET_XVENTANACONDOPS only on 64-bit target

I think option 2 is the simplest yet understandable.

> 
> 
>> +(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")])
>> +(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")])
> We did these as N/n which output n or nothing:
> 
> (define_code_attr n [(eq "n") (ne "")])
> (define_code_attr N [(eq "") (ne "n")])

That's a great idea.  I will stick to "eqz_ventana" and "nez_ventana"
but will change the contents to "n" and "".

> 
> 
>>     ;; Zicond
>>   (define_insn "*czero.."
>> @@ -28,8 +31,15 @@
>>   (const_int 0))
>>     (match_operand:GPR 2 "register_operand"   
>> "r")
>>     (const_int 0)))]
>> -  "TARGET_ZICOND"
>> -  "czero.\t%0,%2,%1"
>> +  "TARGET_ZICOND_LIKE"
>> +  {
>> +    if (TARGET_ZICOND)
>> +  return "czero.\t%0,%2,%1";
>> +    else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
>> +  return "vt.\t%0,%2,%1";
>> +    else
>> +  gcc_unreachable ();
>> +  }
>>   )
> And so the output template ends up like this:
> 
>>   "* return TARGET_ZICOND ? \"czero.\t%0,%2,%1\" :
>> \"vt.maskc\t%0,%2,%1\"; "
> 
> But again, I don't care enough about this to make it a big deal and I'm
> happy to go with your approach.
> 
> 
> 
>> diff --git
>> a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c 
>> b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
>> new file mode 100644
>> index ..992f1425c54f
>> --- /dev/null
>> +++
>> 

Re: [PATCH v2] RISC-V: Fix Zicond ICE on large constants

[Tsukasa OI via Gcc-patches]

On 2023/09/06 10:22, Jeff Law wrote:
> 
> 
> On 9/5/23 06:08, Tsukasa OI wrote:
>> From: Tsukasa OI 
>>
>> Large constant cons and/or alt will trigger ICEs building GCC target
>> libraries (libgomp and libatomic) when the 'Zicond' extension is enabled.
>>
>> For instance, zicond-ice-2.c (new test case in this commit) will cause
>> an ICE when SOME_NUMBER is 0x1000 or larger.  While opposite numbers
>> corresponding cons/alt (two temp2 variables) are checked, cons/alt
>> themselves are not checked and causing 2 ICEs building
>> GCC target libraries as of this writing:
>>
>> 1.  gcc/libatomic/config/posix/lock.c
>> 2.  gcc/libgomp/fortran.c
>>
>> Coercing a large value into a register will fix the issue.
>>
>> It also coerce a large cons into a register on "imm, imm" case (the
>> author
>> could not reproduce but possible to cause an ICE).
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_expand_conditional_move): Force
>> large constant cons/alt into a register.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zicond-ice-2.c: New test.  This is based on
>> an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c
>> but heavily minimized.
> "New test." is sufficient.  No need to change it, just a note going
> forward.
> 
> OK.  Thanks for taking care of this.
> 
> jeff
> 

Thanks for reviewing.  I'll remember that for the next time (I am adding
brief description in Binutils but not *that* long compared to this).

Committing.

Tsukasa

[PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.

And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).

*   czero.eqz == vt.maskc
*   czero.nez == vt.maskcn

This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support.  With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.

The specification for the 'XVentanaCondOps' extension is based on:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'.  It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero..): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero..): Ditto.
(*czero.eqz..opt1): Ditto.
(*czero.nez..opt2): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
modified from zicond-primitiveSemantics.c.
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
from zicond-xor-01.c.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 51 +++
 .../xventanacondops-primitiveSemantics-rv32.c | 45 
 .../xventanacondops-primitiveSemantics.c  | 48 +
 .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +
 9 files changed, 162 insertions(+), 13 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
 
+  {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index b6b5907e111b..a525f679683c 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -321,6 +321,12 @@ enum riscv_entity
 #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
 #define TARGET_XTHEADSYNC((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
 
+#define MASK_XVENTANACONDOPS  (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) 
!= 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && 
TARGET_64BIT))
+
 /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes.  */
 #define TARGET_VECTOR_VLS  
\
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d8f7b4f16ed..eb10f4a3323f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2745,7 +2745,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  *total = COSTS_N_INSNS (1);
  return true;
}
-  else if (TARGET_ZICOND
+  else if 

[PATCH v3 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

PATCH v1:

PATCH v2:


Changes: v1 -> v2
*   Removed bogus opt2 pattern as pointed out in:

note that this is not in the ChangeLog expecting the patch above
applies first.

Changes: v2 -> v3
*   Instead of removing opt2 pattern, fix opt2 pattern:





Tsukasa OI (1):
  RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 51 +++
 .../xventanacondops-primitiveSemantics-rv32.c | 45 
 .../xventanacondops-primitiveSemantics.c  | 48 +
 .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +
 9 files changed, 162 insertions(+), 13 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c


base-commit: 72b639760a891c406725854bfb08132c83f0761a
-- 
2.42.0

[PATCH v2] RISC-V: Fix Zicond ICE on large constants

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

Large constant cons and/or alt will trigger ICEs building GCC target
libraries (libgomp and libatomic) when the 'Zicond' extension is enabled.

For instance, zicond-ice-2.c (new test case in this commit) will cause
an ICE when SOME_NUMBER is 0x1000 or larger.  While opposite numbers
corresponding cons/alt (two temp2 variables) are checked, cons/alt
themselves are not checked and causing 2 ICEs building
GCC target libraries as of this writing:

1.  gcc/libatomic/config/posix/lock.c
2.  gcc/libgomp/fortran.c

Coercing a large value into a register will fix the issue.

It also coerce a large cons into a register on "imm, imm" case (the author
could not reproduce but possible to cause an ICE).

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_conditional_move): Force
large constant cons/alt into a register.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-ice-2.c: New test.  This is based on
an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c
but heavily minimized.
---
 gcc/config/riscv/riscv.cc | 21 +--
 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 ++
 2 files changed, 26 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d8f7b4f16ed..e306d57814be 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3917,6 +3917,11 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  gen_rtx_IF_THEN_ELSE (mode, cond,
CONST0_RTX (mode),
alt)));
+ /* CONS might not fit into a signed 12 bit immediate suitable
+for an addi instruction.  If that's the case, force it
+into a register.  */
+ if (!SMALL_OPERAND (INTVAL (cons)))
+   cons = force_reg (mode, cons);
  riscv_emit_binary (PLUS, dest, dest, cons);
  return true;
}
@@ -3940,11 +3945,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  rtx temp1 = gen_reg_rtx (mode);
  rtx temp2 = gen_int_mode (-1 * INTVAL (cons), mode);
 
- /* TEMP2 might not fit into a signed 12 bit immediate suitable
-for an addi instruction.  If that's the case, force it into
-a register.  */
+ /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate
+suitable for an addi instruction.  If that's the case, force it
+into a register.  */
  if (!SMALL_OPERAND (INTVAL (temp2)))
temp2 = force_reg (mode, temp2);
+ if (!SMALL_OPERAND (INTVAL (cons)))
+   cons = force_reg (mode, cons);
 
  riscv_emit_binary (PLUS, temp1, alt, temp2);
  emit_insn (gen_rtx_SET (dest,
@@ -3986,11 +3993,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  rtx temp1 = gen_reg_rtx (mode);
  rtx temp2 = gen_int_mode (-1 * INTVAL (alt), mode);
 
- /* TEMP2 might not fit into a signed 12 bit immediate suitable
-for an addi instruction.  If that's the case, force it into
-a register.  */
+ /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate
+suitable for an addi instruction.  If that's the case, force it
+into a register.  */
  if (!SMALL_OPERAND (INTVAL (temp2)))
temp2 = force_reg (mode, temp2);
+ if (!SMALL_OPERAND (INTVAL (alt)))
+   alt = force_reg (mode, alt);
 
  riscv_emit_binary (PLUS, temp1, cons, temp2);
  emit_insn (gen_rtx_SET (dest,
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c 
b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
new file mode 100644
index ..ffd8dcb5814e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */
+
+#define SOME_NUMBER 0x1000
+
+unsigned long
+d (unsigned long n)
+{
+  return n > SOME_NUMBER ? SOME_NUMBER : n;
+}

base-commit: 72b639760a891c406725854bfb08132c83f0761a
-- 
2.42.0

Re: [PATCH] RISC-V: Fix Zicond ICE on large constants

[Tsukasa OI via Gcc-patches]

On 2023/09/05 14:27, Jeff Law wrote:
> 
> 
> On 9/4/23 00:45, Kito Cheng wrote:
>> Maybe move the check logic a bit forward? My thought is the logic is
>> already specialized into a few catalogs, (imm, imm), (imm, reg), (reg,
>> reg)... and the logic you put is already in (imm, reg), but it should
>> really move into (reg, reg) case IMO? and move that forward we could
>> prevent add too much logic to redirect the case.
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 2db9c81ac8b..c84509c393b 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -3892,6 +3892,12 @@ riscv_expand_conditional_move (rtx dest, rtx
>> op, rtx cons, rtx alt)
>>   op1 = XEXP (op, 1);
>>     }
>>
>> +  /* CONS might not fit into a signed 12 bit immediate suitable
>> +    for an addi instruction.  If that's the case, force it into
>> +    a register.  */
>> +  if (CONST_INT_P (cons) && !SMALL_OPERAND (INTVAL (cons)))
>> +   cons = force_reg (mode, cons);
>> +
>>    /* 0, reg or 0, imm */
>>    if (cons == CONST0_RTX (mode)
>>   && (REG_P (alt)
> But for the imm, imm case if we force things into regs too early, then
> we'll lose if alt - cons and cons fit in a 12 bit immediate but alt does
> not.
> 
> I think Tsukasa is on the right path here.  I should have checked
> riscv_emit_binary -- I though it handled the out-of-range constant case,
> but looking at it now, it clearly does not.
> 
> I think this implies we need a similar blob of code for the imm, imm
> case for cons.
> 
> Jeff
> 

Okay, adding a check to "imm, imm" case (although I haven't figured out
how to reproduce this case) and will submit the v2.

Tsukasa

Re: [PATCH v2] RISC-V: zicond: Fix opt2 pattern

[Tsukasa OI via Gcc-patches]

Sorry, I want to directly reply to Jeff but I couldn't because I haven't
subscribed to gcc-patches and Jeff's recent reply hasn't archived yet.

Bug confirmed for me.

I tried the full test with following configuration (I found another bug
[ICE] as I submitted a quick fix while testing this and requires
following patch set to be applied; will make a PATCH v2 though):


Possibly, ICE, simulator configuration and/or dirty build tree might be
the reason Jeff couldn't reproduce the bug.

# ZiCond enabled
# Remove "_zicond" to disable ZiCond.
# ${SYSROOT} points to the prebuilt sysroot with
# glibc + libgcc with -march=rv64imafdc -mabi=lp64d
${GCC_SRCDIR}/configure \
--target=riscv64-unknown-linux-gnu \
--prefix=${PREFIX}   \
--with-sysroot=${SYSROOT}\
--with-system-zlib   \
--disable-shared \
--enable-tls \
--enable-languages=c,c++ \
--disable-libmudflap \
--disable-libssp \
--disable-libquadmath\
--disable-libsanitizer   \
--disable-nls\
--disable-bootstrap  \
--disable-multilib   \
--with-tune=rocket   \
--with-arch=rv64imafdc_zicond\
--with-abi=lp64d \
--with-isa-spec=20191213

Then I ran "make; make check RUNTESTFLAGS='--target_board=riscv-sim'".
Note that I configured DejaGnu (riscv-sim.exp) to execute tests with:
"qemu-riscv64 -L ${SYSROOT} -cpu rv64,g=on,x-zicond=on" (QEMU 8.1.0
Linux user emulation).

Warning: abort() on QEMU with Linux user emulation causes QEMU to abort,
too (possibly making many coredumps).

The diff of test failures are as follows.
-: Occurs only when ZiCond is disabled
+: Occurs only when ZiCond is enabled

-FAIL: 30_threads/async/async.cc execution test
+FAIL: gcc.c-torture/execute/pr60003.c   -O1  execution test
+FAIL: gcc.dg/setjmp-3.c execution test
+FAIL: gcc.dg/torture/stackalign/setjmp-3.c   -O1  execution test
+FAIL: gcc.dg/torture/stackalign/setjmp-3.c   -O1 -fpic execution test

I'm not sure why 30_threads/async/async.cc succeeds after enabling the
'Zicond' extension but I am sure that setjmp-3.c failures are caused by
this very bug.

Smaller example (not involving setjmp / longjmp) to reproduce this bug
in my environment is as follows (you *don't* have to apply my patch
above, make all-gcc && make install-gcc overwriting existing RV64 GCC
prefix will work):

> #include 
> 
> __attribute__((noinline, noclone))
> void sample(long* a)
> {
> *a = 1;
> }
> 
> __attribute__((noinline, noclone))
> long foo(long x)
> {
> long a = 0;
> sample(); // a is overwritten to 1.
> if (a == 0)
> return 0;
> else
> return x; // should be always taken
> }
> 
> int main(int argc, char** argv)
> {
> printf("%ld\n", foo(5)); // should print 5
> return 0;
> }

Note that we have to make sure that variables are not easily inferred by
another optimization pass (that's why I needed two functions).

> riscv64-unknown-linux-gnu-gcc -march=rv64gc_zicond -O1 -static a.c
> qemu-riscv64 -cpu rv64,g=on,x-zicond=on ./a.out

printed 0, not 5 as I expected.

I support Vineet's patch set (v2).

Thanks,
Tsukasa

[PATCH] RISC-V: Fix Zicond ICE on large constants

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

Large constant cons and/or alt will trigger ICEs building GCC target
libraries (libgomp and libatomic) when the 'Zicond' extension is enabled.

For instance, zicond-ice-2.c (new test case in this commit) will cause
an ICE when SOME_NUMBER is 0x1000 or larger.  While opposite numbers
corresponding cons/alt (two temp2 variables) are checked, cons/alt
themselves are not checked and causing 2 ICEs building
GCC target libraries as of this writing:

1.  gcc/libatomic/config/posix/lock.c
2.  gcc/libgomp/fortran.c

Coercing a large value into a register will fix the issue.

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_expand_conditional_move): Force
large constant cons/alt into a register.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zicond-ice-2.c: New test.  This is based on
an ICE at libat_lock_n func on gcc/libatomic/config/posix/lock.c
but heavily minimized.
---
 gcc/config/riscv/riscv.cc | 16 ++--
 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c | 11 +++
 2 files changed, 21 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ice-2.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d8f7b4f16ed..cfaa4b6a7720 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3940,11 +3940,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  rtx temp1 = gen_reg_rtx (mode);
  rtx temp2 = gen_int_mode (-1 * INTVAL (cons), mode);
 
- /* TEMP2 might not fit into a signed 12 bit immediate suitable
-for an addi instruction.  If that's the case, force it into
-a register.  */
+ /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate
+suitable for an addi instruction.  If that's the case, force it
+into a register.  */
  if (!SMALL_OPERAND (INTVAL (temp2)))
temp2 = force_reg (mode, temp2);
+ if (!SMALL_OPERAND (INTVAL (cons)))
+   cons = force_reg (mode, cons);
 
  riscv_emit_binary (PLUS, temp1, alt, temp2);
  emit_insn (gen_rtx_SET (dest,
@@ -3986,11 +3988,13 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx 
cons, rtx alt)
  rtx temp1 = gen_reg_rtx (mode);
  rtx temp2 = gen_int_mode (-1 * INTVAL (alt), mode);
 
- /* TEMP2 might not fit into a signed 12 bit immediate suitable
-for an addi instruction.  If that's the case, force it into
-a register.  */
+ /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate
+suitable for an addi instruction.  If that's the case, force it
+into a register.  */
  if (!SMALL_OPERAND (INTVAL (temp2)))
temp2 = force_reg (mode, temp2);
+ if (!SMALL_OPERAND (INTVAL (alt)))
+   alt = force_reg (mode, alt);
 
  riscv_emit_binary (PLUS, temp1, cons, temp2);
  emit_insn (gen_rtx_SET (dest,
diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c 
b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
new file mode 100644
index ..ffd8dcb5814e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */
+
+#define SOME_NUMBER 0x1000
+
+unsigned long
+d (unsigned long n)
+{
+  return n > SOME_NUMBER ? SOME_NUMBER : n;
+}

base-commit: 78f636d979530c8a649262dbd44914bdfb6f7290
-- 
2.42.0

Re: [PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Tsukasa OI via Gcc-patches]

On 2023/08/31 18:10, Kito Cheng wrote:
> Hi Tsukasa:
> 
> I guess you might did something wrong during commit this patch and
> "RISC-V: Add stub support for existing extensions"
> 
> https://github.com/gcc-mirror/gcc/commit/f30d6a48635b5b180e46c51138d0938d33abd942
> 

It's fine.  That patch was a part of "RISC-V: Add stub support for
existing extensions" (the only intent for subset submission was faster
review but the bigger one is accepted earlier than I expected).

Tsukasa

[RFC PATCH v2 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.

And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).

*   czero.eqz == vt.maskc
*   czero.nez == vt.maskcn

This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support.  With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.

The specification for the 'XVentanaCondOps' extension is based on:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'.  It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero..): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero..): Ditto.
(*czero.eqz..opt1): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
modified from zicond-primitiveSemantics.c.
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
from zicond-xor-01.c.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 52 ---
 .../xventanacondops-primitiveSemantics-rv32.c | 45 
 .../xventanacondops-primitiveSemantics.c  | 48 +
 .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +
 9 files changed, 154 insertions(+), 22 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
 
+  {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5ed69abd214d..a4fb0a0a5946 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -319,6 +319,12 @@ enum riscv_entity
 #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
 #define TARGET_XTHEADSYNC((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
 
+#define MASK_XVENTANACONDOPS  (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) 
!= 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && 
TARGET_64BIT))
+
 /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes.  */
 #define TARGET_VECTOR_VLS  
\
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5dc303f89c79..89af39a08190 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2744,7 +2744,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  *total = COSTS_N_INSNS (1);
  return true;
}
-  else if (TARGET_ZICOND
+  else if (TARGET_ZICOND_LIKE
   && outer_code == 

[RFC PATCH v2 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

PATCH v1:


Changes: v1 -> v2
*   Removed bogus opt2 pattern as pointed out in:

note that this is not in the ChangeLog expecting the patch above
applies first.




Tsukasa OI (1):
  RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 52 ---
 .../xventanacondops-primitiveSemantics-rv32.c | 45 
 .../xventanacondops-primitiveSemantics.c  | 48 +
 .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +
 9 files changed, 154 insertions(+), 22 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c


base-commit: 597b9ec69bca8acb7a3d65641c0a730de8b27ed4
-- 
2.42.0

[RFC PATCH] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.

And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).

*   czero.eqz == vt.maskc
*   czero.nez == vt.maskcn

This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support.  With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.

The specification for the 'XVentanaCondOps' extension is based on:


gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'.  It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (movcc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero..): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero..): Ditto.
(*czero.eqz..opt1): Ditto.
(*czero.nez..opt2): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
modified from zicond-primitiveSemantics.c.
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
from zicond-xor-01.c.
---
 gcc/common/config/riscv/riscv-common.cc   |  2 +
 gcc/config/riscv/riscv-opts.h |  6 +++
 gcc/config/riscv/riscv.cc |  4 +-
 gcc/config/riscv/riscv.md |  2 +-
 gcc/config/riscv/riscv.opt|  3 ++
 gcc/config/riscv/zicond.md| 53 +++
 .../xventanacondops-primitiveSemantics-rv32.c | 45 
 .../xventanacondops-primitiveSemantics.c  | 48 +
 .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +
 9 files changed, 163 insertions(+), 14 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"xtheadmempair", _options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
   {"xtheadsync",_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
 
+  {"xventanacondops", _options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5ed69abd214d..a4fb0a0a5946 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -319,6 +319,12 @@ enum riscv_entity
 #define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
 #define TARGET_XTHEADSYNC((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
 
+#define MASK_XVENTANACONDOPS  (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) 
!= 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && 
TARGET_64BIT))
+
 /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes.  */
 #define TARGET_VECTOR_VLS  
\
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2b39a6167442..a3285985e43f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2725,7 +2725,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
  *total = COSTS_N_INSNS (1);
  return true;
}
-  else if (TARGET_ZICOND
+  else if 

[COMMITTED] MAINTAINERS: Add myself to write after approval

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

ChangeLog:

* MAINTAINERS: Add myself.
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 4e706df65226..35f00beebff2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -592,6 +592,7 @@ Carlos O'Donell 

 Peter O'Gorman 
 Patrick O'Neill
 Braden Obrzut  
+Tsukasa Oi 
 Andrea Ornstein
 Maxim Ostapenko

 Jeevitha Palanisamy
-- 
2.42.0

Re: [PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Tsukasa OI via Gcc-patches]

On 2023/08/29 17:42, Kito Cheng wrote:
> LGTM, did you have commit access for GCC repo? you should obtain it if
> you don't have it yet, I think you are already an important member of
> the RISC-V GNU toolchain community :)

Not yet (only Binutils/GDB).  Jeff is mainly merging my changes to the
trunk so far.

Thanks for mentioning and sponsoring me for write access to GCC.  I
truly appreciate that mentioning me as an important member and write
access to the GCC repository will be also helpful.

I'll contact GCC overseers later.

Sincerely,
Tsukasa

> 
> https://gcc.gnu.org/gitwrite.html#authenticated , and you can add me
> to the cc list as your sponsor.
> 
> 
> 
> On Tue, Aug 29, 2023 at 11:42 AM Tsukasa OI via Gcc-patches
>  wrote:
>>
>> From: Tsukasa OI 
>>
>> As the specification states, the 'Zcmt' extension depends on the 'Zca' and
>> 'Zicsr' extensions.  This commit reflects this implication.
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc
>> (riscv_implied_info): Add implication from 'Zcmt' to 'Zicsr'.
>> ---
>>  gcc/common/config/riscv/riscv-common.cc | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc 
>> b/gcc/common/config/riscv/riscv-common.cc
>> index a5b62cda3a09..1315c8a745ec 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -142,6 +142,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
>>{"zcb",  "zca"},
>>{"zcmp", "zca"},
>>{"zcmt", "zca"},
>> +  {"zcmt", "zicsr"},
>>
>>{NULL, NULL}
>>  };
>> --
>> 2.42.0
>>
> 

[PATCH 0/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Tsukasa OI via Gcc-patches]

This is a subset of my patch set
"RISC-V: Add stub support for existing extensions"

for faster review.

Since 'Zcmt' requires 'Zicsr' (and this is a bug unlike other changes in
the patch set above), this small patch is splitted.

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Imply 'Zicsr' from 'Zcmt'

 gcc/common/config/riscv/riscv-common.cc | 1 +
 1 file changed, 1 insertion(+)


base-commit: 818cc9f2d2f3dbbd4004ff85d3125d92d1e430c9
-- 
2.42.0

[PATCH 1/1] RISC-V: Imply 'Zicsr' from 'Zcmt'

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

As the specification states, the 'Zcmt' extension depends on the 'Zca' and
'Zicsr' extensions.  This commit reflects this implication.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implication from 'Zcmt' to 'Zicsr'.
---
 gcc/common/config/riscv/riscv-common.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index a5b62cda3a09..1315c8a745ec 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -142,6 +142,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zcb",  "zca"},
   {"zcmp", "zca"},
   {"zcmt", "zca"},
+  {"zcmt", "zicsr"},
 
   {NULL, NULL}
 };
-- 
2.42.0

[PATCH v3 3/3] RISC-V: Add stub support for existing extensions (unprivileged)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects or programs
with inline assembler, GCC should support almost all extensions that
Binutils support, even if the GCC itself does not touch a thing.

This commit adds stub supported standard unprivileged extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c except not yet
merged 'Zce', 'Zcmp' and 'Zcmt' support).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implications from unprivileged extensions.
(riscv_ext_version_table): Add stub support for all unprivileged
extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-31.c: New test for a stub unprivileged
extension 'Zcb' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc|  1 +
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 ++
 2 files changed, 32 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 8e2b3ba6d621..f142212f2edc 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -142,6 +142,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zcb",  "zca"},
   {"zcmp", "zca"},
   {"zcmt", "zca"},
+  {"zcmt", "zicsr"},
 
   {"smaia", "ssaia"},
   {"smstateen", "ssstateen"},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-31.c 
b/gcc/testsuite/gcc.target/riscv/predef-31.c
new file mode 100644
index ..4ea11442f995
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-31.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcb -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zca)
+#error "__riscv_zca"
+#endif
+
+#if !defined(__riscv_zcb)
+#error "__riscv_zcb"
+#endif
+
+  return 0;
+}
-- 
2.42.0

[PATCH v3 2/3] RISC-V: Add stub support for existing extensions (vendor)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects or programs
with inline assembler, GCC should support almost all extensions that
Binutils support, even if the GCC itself does not touch a thing.

This commit adds stub supported vendor extensions to
riscv_ext_version_table (no riscv_implied_info entries to add; all
information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add stub support for all vendor extensions supported by Binutils.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-30.c: New test for a stub
vendor extension 'XVentanaCondOps'.
---
 gcc/common/config/riscv/riscv-common.cc|  2 ++
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 ++
 2 files changed, 29 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 3502993026d6..8e2b3ba6d621 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -322,6 +322,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
diff --git a/gcc/testsuite/gcc.target/riscv/predef-30.c 
b/gcc/testsuite/gcc.target/riscv/predef-30.c
new file mode 100644
index ..9784b9ce5033
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-30.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_xventanacondops -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_xventanacondops)
+#error "__riscv_xventanacondops"
+#endif
+
+  return 0;
+}
-- 
2.42.0

[PATCH v3 1/3] RISC-V: Add stub support for existing extensions (privileged)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects or programs
with inline assembler, GCC should support almost all extensions that
Binutils support, even if the GCC itself does not touch a thing.

As a start, this commit adds stub supported *privileged* extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implications from privileged extensions.
(riscv_ext_version_table): Add stub support for all privileged
extensions supported by Binutils.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-29.c: New test for a stub privileged
extension 'Smstateen' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc| 18 +++
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 ++
 2 files changed, 53 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index a5b62cda3a09..3502993026d6 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -143,6 +143,14 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zcmp", "zca"},
   {"zcmt", "zca"},
 
+  {"smaia", "ssaia"},
+  {"smstateen", "ssstateen"},
+  {"smepmp", "zicsr"},
+  {"ssaia", "zicsr"},
+  {"sscofpmf", "zicsr"},
+  {"ssstateen", "zicsr"},
+  {"sstc", "zicsr"},
+
   {NULL, NULL}
 };
 
@@ -288,8 +296,18 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"smaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smepmp",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0},
+
+  {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sscofpmf",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sstc",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-29.c 
b/gcc/testsuite/gcc.target/riscv/predef-29.c
new file mode 100644
index ..61c6429be558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-29.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smstateen -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zicsr)
+#error "__riscv_zicsr"
+#endif
+
+#if !defined(__riscv_smstateen)
+#error "__riscv_smstateen"
+#endif
+
+#if !defined(__riscv_ssstateen)
+#error "__riscv_ssstateen"
+#endif
+
+  return 0;
+}
-- 
2.42.0

[PATCH v3 0/3] RISC-V: Add stub support for existing extensions

[Tsukasa OI via Gcc-patches]

PATCH v1:

PATCH v2:



Changes: v1 -> v2 (only in PATCH 3/3)
==

Removed: 'Zvkn' -> 'Zvknha' implication (not to cause test failure)
Added:   'Zfa' -> 'F' implication (just I forgot to add in PATCH v1)


Changes: v2 -> v3 (only in PATCH 3/3)
==

Changed: 'Zcmt' -> 'Zcicsr' to
 'Zcmt' ->  'Zicsr' (fix typo)
Rebased against commit 17c22f466162
("RISC-V: Minimal support for ZC* extensions.").
and commit 30699b999e94
("[PATCH v10] RISC-V: Add support for the Zfa extension").
Slightly modified the commit message, reflecting the background.

As a rebase result, PATCH 3/3 got nearly empty (except a test case).


Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add stub support for existing extensions (privileged)
  RISC-V: Add stub support for existing extensions (vendor)
  RISC-V: Add stub support for existing extensions (unprivileged)

 gcc/common/config/riscv/riscv-common.cc| 21 +
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 ++
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 +
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 +++
 4 files changed, 114 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c


base-commit: 818cc9f2d2f3dbbd4004ff85d3125d92d1e430c9
-- 
2.42.0

[PATCH] RISC-V: Make arch-24.c to test "success" case

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

arch-24.c and arch-25.c are exactly the same and redundant.  The author
suspects that the original author intended to test two base ISAs (RV32I and
RV64I) so this commit changes arch-24.c to test that RV32I+Zcf does not
cause any errors.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/arch-24.c: Test RV32I+Zcf instead.
---
 gcc/testsuite/gcc.target/riscv/arch-24.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/arch-24.c 
b/gcc/testsuite/gcc.target/riscv/arch-24.c
index 3be4ade65a77..af15c3234b5e 100644
--- a/gcc/testsuite/gcc.target/riscv/arch-24.c
+++ b/gcc/testsuite/gcc.target/riscv/arch-24.c
@@ -1,5 +1,3 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+/* { dg-options "-march=rv32i_zcf -mabi=ilp32" } */
 int foo() {}
-/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { 
target *-*-* } 0 } */
-/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" 
{ target *-*-* } 0 } */

base-commit: 818cc9f2d2f3dbbd4004ff85d3125d92d1e430c9
-- 
2.42.0

[PATCH v2] RISC-V: Make PR 102957 tests more comprehensive

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

Commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions and
commit 6f709f79c915a ("[committed] [RISC-V] Fix expected diagnostic messages
in testsuite") "fixed" test failures caused by that change (on pr102957.c,
by testing the error message after the first change).

However, the latter change will partially break the original intent of PR
102957 test case because we wanted to make sure that we can parse a valid
two-letter extension name.

Fortunately, there is a valid two-letter extension name, 'Zk' (standard
scalar cryptography extension superset with NIST algorithm suite).

This commit adds pr102957-2.c to make sure that there will be no errors if
we parse a valid two-letter extension name.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr102957-2.c: New test case using the 'Zk'
extension to continue testing whether we can use valid two-letter
extensions.
---
 gcc/testsuite/gcc.target/riscv/pr102957-2.c | 5 +
 1 file changed, 5 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/pr102957-2.c

diff --git a/gcc/testsuite/gcc.target/riscv/pr102957-2.c 
b/gcc/testsuite/gcc.target/riscv/pr102957-2.c
new file mode 100644
index ..fe6241466354
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr102957-2.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gzk -mabi=lp64" } */
+int foo()
+{
+}

base-commit: 818cc9f2d2f3dbbd4004ff85d3125d92d1e430c9
-- 
2.42.0

Re: [PATCH v2 3/3] RISC-V: Add stub support for existing extensions (unprivileged)

[Tsukasa OI via Gcc-patches]

On 2023/08/29 10:42, Jeff Law wrote:
> 
> 
> On 8/14/23 00:09, Tsukasa OI wrote:
>> From: Tsukasa OI 
>>
>> After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
>> extensions") changed how do we handle unknown extensions, we have no
>> guarantee that we can share the same architectural string with Binutils
>> (specifically, the assembler).
>>
>> To avoid compilation errors on shared Assembler-C/C++ projects, GCC
>> should
>> support almost all extensions that Binutils support, even if the GCC does
>> not touch a thing.
>>
>> This commit adds stub supported standard unprivileged extensions to
>> riscv_ext_version_table and its implications to riscv_implied_info
>> (all information is copied from Binutils' bfd/elfxx-riscv.c except not
>> yet
>> merged 'Zce', 'Zcmp' and 'Zcmt' support).
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc
>> (riscv_implied_info): Add implications from unprivileged extensions.
>> (riscv_ext_version_table): Add stub support for all unprivileged
>> extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/predef-31.c: New test for a stub unprivileged
>> extension 'Zcb' with some implications.
> This series (most likely patch 3/3) seems to break arch-24.c and arch-25.c.
> 
> Please fix and post a V3.
> 
> Jeff
> 

I think it was a hidden merge failure with partial Zc* extensions
support by Jiawei (and I already fixed it in the internal version).
I'll re-review it and submit as v3 if it's okay.

I don't recall exact test cases that failed (when I tested) but looking
at arch-24.c and arch-25.c you pointed out, they have a minor issue
(independent with this patch set).  I'll submit a minor fix for those
files later.

Thanks,
Tsukasa

Re: [RFC PATCH 2/2] RISC-V: Fix documentation of __builtin_riscv_pause

[Tsukasa OI via Gcc-patches]

On 2023/08/29 8:09, Hans-Peter Nilsson wrote:
> On Mon, 28 Aug 2023, Jeff Law via Gcc-patches wrote:
>>
>>
>> On 8/9/23 00:11, Tsukasa OI via Gcc-patches wrote:
>>> From: Tsukasa OI 
>>>
>>> This built-in does not imply the 'Xgnuzihintpausestate' extension.
>>> It does not change architectural state (because all HINTs are prohibited
>>> from doing that).
>>>
>>> gcc/ChangeLog:
>>>
>>> * doc/extend.texi: Fix the description of __builtin_riscv_pause.
>> I've pushed this to the trunk.
> 
> I randomly noticed a typo: "hart", perhaps for "part"?
> Not sure though.
> 
> brgds, H-P
> 

Hi H-P,

As Jeff mentioned you, the word "hart" in the RISC-V world means a
HARdware Thread and commonly used to represent a hardware-based unit of
execution.

Tsukasa

Re: [PATCH] RISC-V: Revive test case PR 102957

[Tsukasa OI via Gcc-patches]

On 2023/08/29 7:01, Jeff Law wrote:
> 
> 
> On 8/11/23 08:29, Tsukasa OI wrote:
>> On 2023/08/11 23:15, Jeff Law wrote:
> 
>>>
>>
>> Originally, it tested that a two letter extension ('Zb') is accepted by
>> GCC (because the background of PR 102957 was GCC assumed multi-letter
>> 'Z' extensions are three letters or more).
>>
>> After rejecting unrecognized extensions, "dg-error" is added **just to
>> avoid the test failure** and that doesn't look right.  Yes, we now don't
>> have an ICE (like in the original report) but after the PR 102957 fix,
>> we just accepted it, not rejecting it.
>>
>> Instead, we have a valid (recognized) two-letter 'Z' extension: 'Zk'.  I
>> think replacing "zb" with "zk" is more correct considering the original
>> bug report (PR 102957) and its assumption.
>>
>> cf. 
> Thanks.  It still seems to me we want to  have two tests here.
> 
> I would suggest leaving pr102957.c alone since that tests that we give a
> proper error for "zb".  Then create a new test that verifies "zk" is
> accepted without error.
> 
> jeff
> 

Okay, that's a great compromise.

I will make v2 to add pr102957-2.c (like so) to reflect my intention and
keep the original pr102957.c.

Thanks,
Tsukasa

Re: [PATCH 1/1] RISC-V: Make "prefetch.i" built-in usable

[Tsukasa OI via Gcc-patches]

On 2023/08/29 6:20, Jeff Law wrote:
> 
> 
> On 8/9/23 21:10, Tsukasa OI via Gcc-patches wrote:
>> From: Tsukasa OI 
>>
>> The "__builtin_riscv_zicbop_cbo_prefetchi" built-in function was terribly
>> broken so that practically unusable.  It emitted "prefetch.i" but with no
>> meaningful arguments.
>>
>> Though incompatible, this commit completely changes the function
>> prototype
>> of this built-in and makes it usable.  To minimize the functionality
>> issues,
>> it renames the built-in to "__builtin_riscv_zicbop_prefetch_i".
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-cmo.def: Fix function prototype.
>> * config/riscv/riscv.md (riscv_prefetchi_): Fix instruction
>> prototype.  Remove possible prefectch type argument
>> * doc/extend.texi: Document __builtin_riscv_zicbop_prefetch_i.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/cmo-zicbop-1.c: Reflect new built-in prototype.
>> * gcc.target/riscv/cmo-zicbop-2.c: Likewise.
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index 688fd697255b..5658c7b7e113 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -3273,9 +3273,8 @@
>>   })
>>     (define_insn "riscv_prefetchi_"
>> -  [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
>> -  (match_operand:X 1 "imm5_operand" "i")]
>> -  UNSPECV_PREI)]
>> +  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
>> +    UNSPECV_PREI)]
>>     "TARGET_ZICBOP"
>>     "prefetch.i\t%a0"
>>   )
> What I would suggest is making a new predicate that accepts either a
> register or a register+offset where the offset fits in a signed 12 bit
> immediate.  Use that for operand 0's predicate and I think this will
> "just work" and cover all the cases supported by the prefetch.i
> instruction.
> 
> Jeff
> 

Seems reasonable.

If we have to break the compatibility anyway, adding an offset argument
is not a bad idea (though I think they will use inline assembly if a
non-zero offset is required).

I will try to add *optional* offset argument (with default value 0) like
 __builtin_speculation_safe_value built-in function in the next version.

Thanks,
Tsukasa

Re: [RFC PATCH 1/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

On 2023/08/29 6:12, Jeff Law wrote:
> 
> 
> On 8/9/23 00:11, Tsukasa OI via Gcc-patches wrote:
>> From: Tsukasa OI 
>>
>> The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
>> (in the assembler).  However, GCC emits "pause" unconditionally, making
>> an assembler error while compiling code with __builtin_riscv_pause while
>> the 'Zihintpause' extension disabled.
>>
>> However, the "pause" instruction code (0x010f) is a HINT and emitting
>> its instruction code is safe in any environment.
>>
>> This commit implements handling for the 'Zihintpause' extension and emits
>> ".insn 0x010f" instead of "pause" only if the extension is disabled
>> (making the diagnostics better).
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc
>> (riscv_ext_version_table): Implement the 'Zihintpause' extension,
>> version 2.0.  (riscv_ext_flag_table) Add 'Zihintpause' handling.
>> * config/riscv/riscv-builtins.cc: Remove availability predicate
>> "always" and add "hint_pause" and "hint_pause_pseudo", corresponding
>> the existence of the 'Zihintpause' extension.
>> (riscv_builtins) Split builtin implementation depending on the
>> existence of the 'Zihintpause' extension.
>> * config/riscv/riscv-opts.h
>> (MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New.
>> * config/riscv/riscv.md (riscv_pause): Make it only available when
>> the 'Zihintpause' extension is enabled.  (riscv_pause_insn) New
>> "pause" implementation when the 'Zihintpause' extension is disabled.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/builtin_pause.c: Removed.
>> * gcc.target/riscv/zihintpause.c:
>> New test when the 'Zihintpause' extension is enabled.
>> * gcc.target/riscv/zihintpause-noarch.c:
>> New test when the 'Zihintpause' extension is disabled.
> So I cleaned this up a bit per the list discussion and pushed the final
> result.  Hopefully I didn't goof anything too badly ;-)  The net is we
> emit "pause" or a suitable .insn based on TARGET_ZIHINTPAUSE.
> 
> Jeff

Thanks!  I had having a problem to type words through the keyboard for a
while and I appreciate doing that instead of me (your modifications were
mostly "I would do so too" ones).

Also, it seems that I will no longer need to ask you to remove leading
"[PATCH xxx]" (not just the commit title is not my intention, I worried
that you have been doing something inefficient [other than "git am"]).

Tsukasa

[PATCH 2/2] RISC-V: Add quotes to #error messages (all)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

In commit 1aaf3a64e92a ("[PATCH] RISC-V: Deduplicate #error messages in
testsuite"), the author made a mistake to miss the test after adding
quotes around extension names.  To avoid future errors and for consistency
with other #error uses in the RISC-V testsuite, this commit quotes all
unquoted #error messages.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/xtheadba.c: Quote unquoted #error message.
* gcc.target/riscv/xtheadbb.c: Ditto.
* gcc.target/riscv/xtheadbs.c: Ditto.
* gcc.target/riscv/xtheadcmo.c: Ditto.
* gcc.target/riscv/xtheadcondmov.c: Ditto.
* gcc.target/riscv/xtheadfmemidx.c: Ditto.
* gcc.target/riscv/xtheadfmv.c: Ditto.
* gcc.target/riscv/xtheadint.c: Ditto.
* gcc.target/riscv/xtheadmac.c: Ditto.
* gcc.target/riscv/xtheadmemidx.c: Ditto.
* gcc.target/riscv/xtheadmempair.c: Ditto.
* gcc.target/riscv/xtheadsync.c: Ditto.
* gcc.target/riscv/zawrs.c: Ditto.
* gcc.target/riscv/zvbb.c: Ditto.
* gcc.target/riscv/zvbc.c: Ditto.
* gcc.target/riscv/zvkg.c: Ditto.
* gcc.target/riscv/zvkned.c: Ditto.
* gcc.target/riscv/zvknha.c: Ditto.
* gcc.target/riscv/zvknhb.c: Ditto.
* gcc.target/riscv/zvksed.c: Ditto.
* gcc.target/riscv/zvksh.c: Ditto.
* gcc.target/riscv/zvkt.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/xtheadba.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadbb.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadbs.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadint.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadmac.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadmempair.c | 2 +-
 gcc/testsuite/gcc.target/riscv/xtheadsync.c| 2 +-
 gcc/testsuite/gcc.target/riscv/zawrs.c | 2 +-
 gcc/testsuite/gcc.target/riscv/zvbb.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/zvbc.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/zvkg.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/zvkned.c| 2 +-
 gcc/testsuite/gcc.target/riscv/zvknha.c| 2 +-
 gcc/testsuite/gcc.target/riscv/zvknhb.c| 2 +-
 gcc/testsuite/gcc.target/riscv/zvksed.c| 2 +-
 gcc/testsuite/gcc.target/riscv/zvksh.c | 2 +-
 gcc/testsuite/gcc.target/riscv/zvkt.c  | 2 +-
 22 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba.c 
b/gcc/testsuite/gcc.target/riscv/xtheadba.c
index 14cdb1ffe2eb..64ad56011884 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadba.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadba.c
@@ -3,7 +3,7 @@
 /* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */
 
 #ifndef __riscv_xtheadba
-#error Feature macro not defined
+#error "Feature macro not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb.c 
b/gcc/testsuite/gcc.target/riscv/xtheadbb.c
index 66988abf2213..803111b03fb2 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadbb.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbb.c
@@ -3,7 +3,7 @@
 /* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */
 
 #ifndef __riscv_xtheadbb
-#error Feature macro not defined
+#error "Feature macro not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs.c 
b/gcc/testsuite/gcc.target/riscv/xtheadbs.c
index 808d7378a7be..ad9fba525971 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadbs.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbs.c
@@ -3,7 +3,7 @@
 /* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */
 
 #ifndef __riscv_xtheadbs
-#error Feature macro not defined
+#error "Feature macro not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcmo.c 
b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c
index eab8fef421cd..fc13754fe521 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcmo.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c
@@ -3,7 +3,7 @@
 /* { dg-options "-march=rv64gc_xtheadcmo" { target { rv64 } } } */
 
 #ifndef __riscv_xtheadcmo
-#error Feature macro not defined
+#error "Feature macro not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c 
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
index a239c3f9f46e..ad8a777ab2cc 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c
@@ -3,7 +3,7 @@
 /* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
 
 #ifndef __riscv_xtheadcondmov
-#error Feature macro not defined
+#error "Feature macro not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c 
b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c
index e450c5e5c5ac..1617d9475942 

[PATCH 1/2] RISC-V: Add quotes to #error messages

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

In commit 1aaf3a64e92a ("[PATCH] RISC-V: Deduplicate #error messages in
testsuite"), the author made a mistake to miss the test after adding
quotes around extension names.  To avoid future errors and for consistency
with other #error uses in the RISC-V testsuite, this commit quotes #error
messages where necessary to avoid current test case failures.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zvkn.c: Quote #error messages.
* gcc.target/riscv/zvkn-1.c: Ditto.
* gcc.target/riscv/zvknc.c: Ditto.
* gcc.target/riscv/zvknc-1.c: Ditto.
* gcc.target/riscv/zvknc-2.c: Ditto.
* gcc.target/riscv/zvkng.c: Ditto.
* gcc.target/riscv/zvkng-1.c: Ditto.
* gcc.target/riscv/zvkng-2.c: Ditto.
* gcc.target/riscv/zvks.c: Ditto.
* gcc.target/riscv/zvks-1.c: Ditto.
* gcc.target/riscv/zvksc.c: Ditto.
* gcc.target/riscv/zvksc-1.c: Ditto.
* gcc.target/riscv/zvksc-2.c: Ditto.
* gcc.target/riscv/zvksg.c: Ditto.
* gcc.target/riscv/zvksg-1.c: Ditto.
* gcc.target/riscv/zvksg-2.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/zvkn-1.c  | 10 +-
 gcc/testsuite/gcc.target/riscv/zvkn.c| 10 +-
 gcc/testsuite/gcc.target/riscv/zvknc-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvknc-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvknc.c   | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvkng-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvkng-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvkng.c   | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvks-1.c  | 10 +-
 gcc/testsuite/gcc.target/riscv/zvks.c| 10 +-
 gcc/testsuite/gcc.target/riscv/zvksc-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksc-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksc.c   | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksg-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksg-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksg.c   | 14 +++---
 16 files changed, 104 insertions(+), 104 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/zvkn-1.c 
b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
index 84a3b577a496..23b255b47790 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
@@ -3,23 +3,23 @@
 /* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt" { target { rv32 } } } 
*/
 
 #ifndef __riscv_zvkn
-#error Feature macro for `Zvkn' not defined
+#error "Feature macro for `Zvkn' not defined"
 #endif
 
 #ifndef __riscv_zvkned
-#error Feature macro for `Zvkned' not defined
+#error "Feature macro for `Zvkned' not defined"
 #endif
 
 #ifndef __riscv_zvknhb
-#error Feature macro for `Zvknhb' not defined
+#error "Feature macro for `Zvknhb' not defined"
 #endif
 
 #ifndef __riscv_zvbb
-#error Feature macro for `Zvbb' not defined
+#error "Feature macro for `Zvbb' not defined"
 #endif
 
 #ifndef __riscv_zvkt
-#error Feature macro for `Zvkt' not defined
+#error "Feature macro for `Zvkt' not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/zvkn.c 
b/gcc/testsuite/gcc.target/riscv/zvkn.c
index b42c1881b628..0047ebdede6f 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn.c
@@ -3,23 +3,23 @@
 /* { dg-options "-march=rv32gc_zvkn" { target { rv32 } } } */
 
 #ifndef __riscv_zvkn
-#error Feature macro for `Zvkn' not defined
+#error "Feature macro for `Zvkn' not defined"
 #endif
 
 #ifndef __riscv_zvkned
-#error Feature macro for `Zvkned' not defined
+#error "Feature macro for `Zvkned' not defined"
 #endif
 
 #ifndef __riscv_zvknhb
-#error Feature macro for `Zvknhb' not defined
+#error "Feature macro for `Zvknhb' not defined"
 #endif
 
 #ifndef __riscv_zvbb
-#error Feature macro for `Zvbb' not defined
+#error "Feature macro for `Zvbb' not defined"
 #endif
 
 #ifndef __riscv_zvkt
-#error Feature macro for `Zvkt' not defined
+#error "Feature macro for `Zvkt' not defined"
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/zvknc-1.c 
b/gcc/testsuite/gcc.target/riscv/zvknc-1.c
index 5c456a6add78..d8a84c021180 100644
--- a/gcc/testsuite/gcc.target/riscv/zvknc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zvknc-1.c
@@ -3,31 +3,31 @@
 /* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt_zvbc" { target { rv32 } 
} } */
 
 #ifndef __riscv_zvknc
-#error Feature macro for `Zvknc' not defined
+#error "Feature macro for `Zvknc' not defined"
 #endif
 
 #ifndef __riscv_zvkn
-#error Feature macro for `Zvkn' not defined
+#error "Feature macro for `Zvkn' not defined"
 #endif
 
 #ifndef __riscv_zvkned
-#error Feature macro for `Zvkned' not defined
+#error "Feature macro for `Zvkned' not defined"
 #endif
 
 #ifndef __riscv_zvknhb
-#error Feature macro for `Zvknhb' not defined
+#error "Feature macro for `Zvknhb' not defined"
 #endif
 
 #ifndef __riscv_zvbb
-#error Feature macro for `Zvbb' not defined
+#error "Feature 

Re: [2/2] RISC-V: Constant FP Optimization with 'Zfa'

[Tsukasa OI via Gcc-patches]

On 2023/08/15 12:38, Tsukasa OI wrote:
> On 2023/08/14 21:51, Jin Ma wrote:
>> Hi Tsukasa,
>>   What a coincidence, I also implemented zfa extension, which also includes 
>> fli related instructions :)
> 
> Hi, I'm glad to know that someone is working on this extension more
> comprehensively (especially when "someone" is an experienced GCC
> contributor).  I prefer your patch set in general and glad to learn from
> your patch set and your response that my approach was not *that* bad as
> I expected.
> 
> When a new extension gets available, I will be more confident making a
> patch set for GCC (as I already do in GNU Binutils).
> 
>>
>> links: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627294.html
>>
>>> +  if (!TARGET_HARD_FLOAT || !TARGET_ZFA)
>>> +return result;
>>> +  switch (GET_MODE (x))
>>> +{
>>> +case HFmode:
>>> +  /* Not only 'Zfhmin', either 'Zfh' or 'Zvfh' is required.  */
>>> +  if (!TARGET_ZFH && !TARGET_ZVFH)
>>
>> When Zvfh means that zfh is also on, so there may be no need to judge
>> the TARGET_ZVFH here. By the way,the format here seems wrong, maybe 'tab'
>> is needed for alignment?
> 
> For indentation, I believe this is okay considering 3 indent (soft tab)
> from the top (meaning 6 spaces).
> 
> For specification requirements, I think I'm correct.
> 
> The spec says that 'Zvfh' depends on 'Zve32f' and 'Zfhmin'.  'Zfhmin' is
> a conversion-only 'Zfh' subset ('Zve32f' doesn't require any
> FP16-related extensions).
> 
> Note that "fli.h" requires 'Zfa' and ('Zfh' and/or 'Zvfh').
> 
> So, 'Zfh' alone will not be sufficient to check requirements to the
> "fli.h" instruction.  So, checking TARGET_ZFH || TARGET_ZVFH (for
> existence of the "fli.h") should be correct and I think your patch needs
> to be changed "in the long term".
> 
> "In the long term" means that, current GNU Binutils has a bug which
> "fli.h" requires 'Zfa' and 'Zfh' ('Zfa' and 'Zvfh' does not work).
> My initial 'Zfa' proposal (improved by Christoph Müllner and upstreamed
> into master) intentionally ignored this case because I assumed that
> approval/ratification of 'Zvfh' will take some time and we have a time
> to fix before a release of Binutils following approval of both 'Zfa' and
> 'Zvfh' (it turned out to be wrong).
> 
> cf. 
> 
> So, "fixing" this part (on your patch) alone will not make the program
> work (on the simulator) because current buggy GNU Binutils won't accept
> it.  I'm working on it on the GNU Binutils side.

Okay, the bug is fixed on GNU Binutils (master) and waiting approval
from the release maintainer (for binutils-2_41-branch).

Thanks,
Tsukasa

> 
>>
>>> +   return result;
>>> +  break;
>>> +case SFmode: break;
>>> +case DFmode: break;
>>
>> Maybe we still have to judge TARGET_DOUBLE_FLOAT?
> 
> Indeed.  I just missed that.
> 
>>
>>> +default: return result;
>>> +}
>>> +
>>> +  if (!CONST_DOUBLE_P (x))
>>> +return result;
>>
>> I think it might be better to judge whether x satisfies the CONST_DOUBLE_P
>> before switch (GET_MODE (x)) above.
> 
> That's correct.  I think that's a part of leftover when I'm experimenting.
> 
>>
>>> +
>>> +  r = *CONST_DOUBLE_REAL_VALUE (x);
>>> +
>>> +  if (REAL_VALUE_ISNAN (r))
>>> +{
>>> +  long reprs[2] = { 0 };
>>> +  /* Compare with canonical NaN.  */
>>> +  switch (GET_MODE (x))
>>> +   {
>>> +   case HFmode:
>>> + reprs[0] = real_to_target (NULL, ,
>>> +float_mode_for_size (16).require ());
>>> + /* 0x7e00: Canonical NaN for binary16.  */
>>> + if (reprs[0] != 0x7e00)
>>> +   return result;
>>> + break;
>>> +   case SFmode:
>>> + reprs[0] = real_to_target (NULL, ,
>>> +float_mode_for_size (32).require ());
>>> + /* 0x7fc0: Canonical NaN for binary32.  */
>>> + if (reprs[0] != 0x7fc0)
>>> +   return result;
>>> + break;
>>> +   case DFmode:
>>> + real_to_target (reprs, , float_mode_for_size (64).require ());
>>> + if (FLOAT_WORDS_BIG_ENDIAN)
>>> +   std::swap (reprs[0], reprs[1]);
>>> + /* 0x7ff8_: Canonical NaN for binary64.  */
>>> + if (reprs[0] != 0 || reprs[1] != 0x7ff8)
>>> +   return result;
>>> + break;
>>> +   default:
>>> + gcc_unreachable ();
>>> +   }
>>> +  result.type = RISCV_FLOAT_CONST_NAN;
>>> +  result.valid = true;
>>> +  return result;
>>> +}
>>> +  else if (REAL_VALUE_ISINF (r))
>>> +{
>>> +  if (REAL_VALUE_NEGATIVE (r))
>>> +   return result;
>>> +  result.type = RISCV_FLOAT_CONST_INF;
>>> +  result.valid = true;
>>> +  return result;
>>> +}
>>> +
>>> +  bool sign = REAL_VALUE_NEGATIVE (r);
>>> +  result.sign = sign;
>>> +
>>> +  r = real_value_abs ();
>>> +  /* GCC internally does not use IEEE754-like encoding (where normalized
>>> + significands are in the range [1, 2).  GCC uses [0.5, 1) (see 
>>> 

Re: [2/2] RISC-V: Constant FP Optimization with 'Zfa'

[Tsukasa OI via Gcc-patches]

On 2023/08/14 21:51, Jin Ma wrote:
> Hi Tsukasa,
>   What a coincidence, I also implemented zfa extension, which also includes 
> fli related instructions :)

Hi, I'm glad to know that someone is working on this extension more
comprehensively (especially when "someone" is an experienced GCC
contributor).  I prefer your patch set in general and glad to learn from
your patch set and your response that my approach was not *that* bad as
I expected.

When a new extension gets available, I will be more confident making a
patch set for GCC (as I already do in GNU Binutils).

> 
> links: https://gcc.gnu.org/pipermail/gcc-patches/2023-August/627294.html
> 
>> +  if (!TARGET_HARD_FLOAT || !TARGET_ZFA)
>> +return result;
>> +  switch (GET_MODE (x))
>> +{
>> +case HFmode:
>> +  /* Not only 'Zfhmin', either 'Zfh' or 'Zvfh' is required.  */
>> +  if (!TARGET_ZFH && !TARGET_ZVFH)
> 
> When Zvfh means that zfh is also on, so there may be no need to judge
> the TARGET_ZVFH here. By the way,the format here seems wrong, maybe 'tab'
> is needed for alignment?

For indentation, I believe this is okay considering 3 indent (soft tab)
from the top (meaning 6 spaces).

For specification requirements, I think I'm correct.

The spec says that 'Zvfh' depends on 'Zve32f' and 'Zfhmin'.  'Zfhmin' is
a conversion-only 'Zfh' subset ('Zve32f' doesn't require any
FP16-related extensions).

Note that "fli.h" requires 'Zfa' and ('Zfh' and/or 'Zvfh').

So, 'Zfh' alone will not be sufficient to check requirements to the
"fli.h" instruction.  So, checking TARGET_ZFH || TARGET_ZVFH (for
existence of the "fli.h") should be correct and I think your patch needs
to be changed "in the long term".

"In the long term" means that, current GNU Binutils has a bug which
"fli.h" requires 'Zfa' and 'Zfh' ('Zfa' and 'Zvfh' does not work).
My initial 'Zfa' proposal (improved by Christoph Müllner and upstreamed
into master) intentionally ignored this case because I assumed that
approval/ratification of 'Zvfh' will take some time and we have a time
to fix before a release of Binutils following approval of both 'Zfa' and
'Zvfh' (it turned out to be wrong).

cf. 

So, "fixing" this part (on your patch) alone will not make the program
work (on the simulator) because current buggy GNU Binutils won't accept
it.  I'm working on it on the GNU Binutils side.

> 
>> +return result;
>> +  break;
>> +case SFmode: break;
>> +case DFmode: break;
> 
> Maybe we still have to judge TARGET_DOUBLE_FLOAT?

Indeed.  I just missed that.

> 
>> +default: return result;
>> +}
>> +
>> +  if (!CONST_DOUBLE_P (x))
>> +return result;
> 
> I think it might be better to judge whether x satisfies the CONST_DOUBLE_P
> before switch (GET_MODE (x)) above.

That's correct.  I think that's a part of leftover when I'm experimenting.

> 
>> +
>> +  r = *CONST_DOUBLE_REAL_VALUE (x);
>> +
>> +  if (REAL_VALUE_ISNAN (r))
>> +{
>> +  long reprs[2] = { 0 };
>> +  /* Compare with canonical NaN.  */
>> +  switch (GET_MODE (x))
>> +{
>> +case HFmode:
>> +  reprs[0] = real_to_target (NULL, ,
>> + float_mode_for_size (16).require ());
>> +  /* 0x7e00: Canonical NaN for binary16.  */
>> +  if (reprs[0] != 0x7e00)
>> +return result;
>> +  break;
>> +case SFmode:
>> +  reprs[0] = real_to_target (NULL, ,
>> + float_mode_for_size (32).require ());
>> +  /* 0x7fc0: Canonical NaN for binary32.  */
>> +  if (reprs[0] != 0x7fc0)
>> +return result;
>> +  break;
>> +case DFmode:
>> +  real_to_target (reprs, , float_mode_for_size (64).require ());
>> +  if (FLOAT_WORDS_BIG_ENDIAN)
>> +std::swap (reprs[0], reprs[1]);
>> +  /* 0x7ff8_: Canonical NaN for binary64.  */
>> +  if (reprs[0] != 0 || reprs[1] != 0x7ff8)
>> +return result;
>> +  break;
>> +default:
>> +  gcc_unreachable ();
>> +}
>> +  result.type = RISCV_FLOAT_CONST_NAN;
>> +  result.valid = true;
>> +  return result;
>> +}
>> +  else if (REAL_VALUE_ISINF (r))
>> +{
>> +  if (REAL_VALUE_NEGATIVE (r))
>> +return result;
>> +  result.type = RISCV_FLOAT_CONST_INF;
>> +  result.valid = true;
>> +  return result;
>> +}
>> +
>> +  bool sign = REAL_VALUE_NEGATIVE (r);
>> +  result.sign = sign;
>> +
>> +  r = real_value_abs ();
>> +  /* GCC internally does not use IEEE754-like encoding (where normalized
>> + significands are in the range [1, 2).  GCC uses [0.5, 1) (see real.cc).
>> + So, this exponent_p1 variable equals IEEE754 unbiased exponent + 1.  */
>> +  int exponent_p1 = REAL_EXP ();
>> +
>> +  /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
>> + highest (sign) bit, with a fixed binary point at bit point_pos.
>> + m1 holds the low part of the mantissa, m2 

Re: [PATCH 0/2] RISC-V: Constant FP Optimization with 'Zfa'

[Tsukasa OI via Gcc-patches]

Oh my, I forgot to change the subject of PATCH 0/2.
That should have been "RISC-V: Constant FP Optimization with 'Zfa'", the
same subject as PATCH 2/2.

Sorry for confusion!

On 2023/08/14 14:32, Tsukasa OI wrote:
> Hello,
> 
> and... I think this might be my first *large* patch set for GCC
> contribution and definitely the first one to touch the machine description.
> 
> So, please review it carefully.
> 
> 
> Background
> ===
> 
> This patch set adds an optimization to FP constant initialization using a
> FLI instruction, which is a part of the 'Zfa' extension which provides
> additional floating-point instructions.
> 
> FLI instructions ("fli.h" for binary16, "fli.s" for binary32, "fli.d" for
> binary64 and "fli.q" for binary128 [which can be ignored because current
> GCC for RISC-V does not natively support binary128]) provide an
> load-immediate operation for following 32 immediates.
> 
> | Binary Encoding | Immediate (and its part of binary representation) |
> | --- | --|
> |`0` ( 0) | -1.0  (-0b1.00 * 2^(+ 0)) |
> |`1` ( 1) | Minimum positive normal value |
> | | sign=[0] exponent=[0..01] significand=[000..000]  |
> |`00010` ( 2) | 1.00*2^(-16)  (+0b1.00 * 2^(-16)) |
> |`00011` ( 3) | 1.00*2^(-15)  (+0b1.00 * 2^(-15)) |
> |`00100` ( 4) | 1.00*2^(- 8)  (+0b1.00 * 2^(- 8)) |
> |`00101` ( 5) | 1.00*2^(- 7)  (+0b1.00 * 2^(- 7)) |
> |`00110` ( 6) | 1.00*2^(- 4)  (+0b1.00 * 2^(- 4)) = 0.0625|
> |`00111` ( 7) | 1.00*2^(- 3)  (+0b1.00 * 2^(- 3)) = 0.125 |
> |`01000` ( 8) | 1.00*2^(- 2)  (+0b1.00 * 2^(- 2)) : 0.25  |
> |`01001` ( 9) | 1.25*2^(- 2)  (+0b1.01 * 2^(- 2)) : 0.3125|
> |`01010` (10) | 1.50*2^(- 2)  (+0b1.10 * 2^(- 2)) : 0.375 |
> |`01011` (11) | 1.75*2^(- 2)  (+0b1.11 * 2^(- 2)) : 0.4375|
> |`01100` (12) | 1.00*2^(- 1)  (+0b1.00 * 2^(- 1)) : 0.5   |
> |`01101` (13) | 1.25*2^(- 1)  (+0b1.01 * 2^(- 1)) : 0.625 |
> |`01110` (14) | 1.50*2^(- 1)  (+0b1.10 * 2^(- 1)) : 0.75  |
> |`0` (15) | 1.75*2^(- 1)  (+0b1.11 * 2^(- 1)) : 0.875 |
> |`1` (16) | 1.00*2^(+ 0)  (+0b1.00 * 2^(+ 0)) : 1.0   |
> |`10001` (17) | 1.25*2^(+ 0)  (+0b1.01 * 2^(+ 0)) : 1.25  |
> |`10010` (18) | 1.50*2^(+ 0)  (+0b1.10 * 2^(+ 0)) : 1.5   |
> |`10011` (19) | 1.75*2^(+ 0)  (+0b1.11 * 2^(+ 0)) : 1.75  |
> |`10100` (20) | 1.00*2^(+ 1)  (+0b1.00 * 2^(+ 1)) : 2.0   |
> |`10101` (21) | 1.25*2^(+ 1)  (+0b1.01 * 2^(+ 1)) : 2.5   |
> |`10110` (22) | 1.50*2^(+ 1)  (+0b1.10 * 2^(+ 1)) : 3.0   |
> |`10111` (23) | 1.00*2^(+ 2)  (+0b1.00 * 2^(+ 2)) = 4 |
> |`11000` (24) | 1.00*2^(+ 3)  (+0b1.00 * 2^(+ 3)) = 8 |
> |`11001` (25) | 1.00*2^(+ 4)  (+0b1.00 * 2^(+ 4)) = 16|
> |`11010` (26) | 1.00*2^(+ 7)  (+0b1.00 * 2^(+ 7)) = 128   |
> |`11011` (27) | 1.00*2^(+ 8)  (+0b1.00 * 2^(+ 8)) = 256   |
> |`11100` (28) | 1.00*2^(+15)  (+0b1.00 * 2^(+15)) = 32768 |
> |`11101` (29) | 1.00*2^(+16)  (+0b1.00 * 2^(+16)) = 65536 |
> | | On "fli.h", this is equivalent to positive inf.   |
> |`0` (30) | Positive infinity |
> | | sign=[0] exponent=[1..11] significand=[000..000]  |
> |`1` (31) | Canonical NaN (positive, quiet and zero payload)  |
> | | sign=[0] exponent=[1..11] significand=[100..000]  |
> 
> Currently, initializing a FP constant (except zero) involves memory and its
> use can be reduced by FLI instructions.
> 
> We may have a room to generate much complex constants with multiple FLI
> instructions (e.g. like long integer constants) but for starter, we can
> begin with optimizing one FP constant initialization with one FLI
> instruction (and because FP arithmetic often requires larger latency,
> benefits of making multiple FLI sequence is not high compared to integers).
> 
> 
> FLI FP constant checking
> =
> 
> An instruction with a similar role to RISC-V's FLI instructions is the Arm/
> AArch64's vmov.f32 instruction. It provides a load-immediate operation for
> constant that can be represented in the following form:
> 
>> (-1)^s * 0b1. * 2^r   (where -3 <= r <= +4; fits in 3-bits)
> 
> This patch is largely influenced by AArch64's handling but
> compared to this, handling RISC-V's FLI FP constant can be a little tricky.
> 
> *   FLI normally generates only values with sign bit 0 except the binary
> encoding 0 (which loads -1.0 with sign bit 1).
> *   Not only finite values, FLI can generate positive infinity and
> canonical NaN.
> *   Because FLI can generate canonical NaN, handling NaN is preferred 

Re: [PATCH v2 0/3] RISC-V: Add stub support for existing extensions

[Tsukasa OI via Gcc-patches]

Hi,

I'll explain a little more background.

A major case which this patch set will be required is when a developer
use inline assembly for instructions not yet natively supported by GCC
or will not be supported as intrinsics.

On such cases, GCC should at least accept corresponding extension via
-march (although there's a workaround using ".option" directives in the
inline assembly but that's tedious).

Thanks,
Tsukasa


On 2023/08/14 15:09, Tsukasa OI wrote:
> PATCH v1:
> 
> 
> 
> Changes: v1 -> v2 (only in PATCH 3/3)
> ==
> 
> Removed: 'Zvkn' -> 'Zvknha' implication (not to cause test failure)
> Added:   'Zfa' -> 'F' implication (just I forgot to add in PATCH v1)
> 
> 
> Thanks,
> Tsukasa
> 
> 
> 
> 
> Tsukasa OI (3):
>   RISC-V: Add stub support for existing extensions (privileged)
>   RISC-V: Add stub support for existing extensions (vendor)
>   RISC-V: Add stub support for existing extensions (unprivileged)
> 
>  gcc/common/config/riscv/riscv-common.cc| 44 ++
>  gcc/testsuite/gcc.target/riscv/predef-29.c | 35 +
>  gcc/testsuite/gcc.target/riscv/predef-30.c | 27 +
>  gcc/testsuite/gcc.target/riscv/predef-31.c | 31 +++
>  4 files changed, 137 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c
> 
> 
> base-commit: 614052dd4ea083e086712809c754ffebd9361316

[PATCH v2 2/3] RISC-V: Add stub support for existing extensions (vendor)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

This commit adds stub supported vendor extensions to
riscv_ext_version_table (no riscv_implied_info entries to add; all
information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add stub support for all vendor extensions supported by Binutils.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-30.c: New test for a stub
vendor extension 'XVentanaCondOps'.
---
 gcc/common/config/riscv/riscv-common.cc|  2 ++
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 ++
 2 files changed, 29 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 91b0316acfea..0c351105e015 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -298,6 +298,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
diff --git a/gcc/testsuite/gcc.target/riscv/predef-30.c 
b/gcc/testsuite/gcc.target/riscv/predef-30.c
new file mode 100644
index ..9784b9ce5033
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-30.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_xventanacondops -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_xventanacondops)
+#error "__riscv_xventanacondops"
+#endif
+
+  return 0;
+}
-- 
2.41.0

[PATCH v2 1/3] RISC-V: Add stub support for existing extensions (privileged)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

As a start, this commit adds stub supported *privileged* extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implications from privileged extensions.
(riscv_ext_version_table): Add stub support for all privileged
extensions supported by Binutils.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-29.c: New test for a stub privileged
extension 'Smstateen' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc| 18 +++
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 ++
 2 files changed, 53 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 21f83f26371f..91b0316acfea 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -130,6 +130,14 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
 
+  {"smaia", "ssaia"},
+  {"smstateen", "ssstateen"},
+  {"smepmp", "zicsr"},
+  {"ssaia", "zicsr"},
+  {"sscofpmf", "zicsr"},
+  {"ssstateen", "zicsr"},
+  {"sstc", "zicsr"},
+
   {NULL, NULL}
 };
 
@@ -264,8 +272,18 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"smaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smepmp",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0},
+
+  {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sscofpmf",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sstc",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-29.c 
b/gcc/testsuite/gcc.target/riscv/predef-29.c
new file mode 100644
index ..61c6429be558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-29.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smstateen -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zicsr)
+#error "__riscv_zicsr"
+#endif
+
+#if !defined(__riscv_smstateen)
+#error "__riscv_smstateen"
+#endif
+
+#if !defined(__riscv_ssstateen)
+#error "__riscv_ssstateen"
+#endif
+
+  return 0;
+}
-- 
2.41.0

[PATCH v2 3/3] RISC-V: Add stub support for existing extensions (unprivileged)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

This commit adds stub supported standard unprivileged extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c except not yet
merged 'Zce', 'Zcmp' and 'Zcmt' support).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implications from unprivileged extensions.
(riscv_ext_version_table): Add stub support for all unprivileged
extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-31.c: New test for a stub unprivileged
extension 'Zcb' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc| 24 +
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 ++
 2 files changed, 55 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0c351105e015..27e9072899bf 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -121,6 +121,20 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvksg", "zvks"},
   {"zvksg", "zvkg"},
 
+  {"zcb", "zca"},
+  {"zcd", "zca"},
+  {"zcd", "d"},
+  {"zcf", "zca"},
+  {"zcf", "f"},
+  {"zce", "zca"},
+  {"zce", "zcb"},
+  {"zce", "zcmp"},
+  {"zce", "zcmt"},
+  {"zcmp", "zca"},
+  {"zcmt", "zca"},
+  {"zcmt", "zcicsr"},
+
+  {"zfa", "f"},
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   {"zvfhmin", "zve32f"},
@@ -197,6 +211,14 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zca",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zce",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcf",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -219,6 +241,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
 
   {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -265,6 +288,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfa",   ISA_SPEC_CLASS_NONE, 0, 1},
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-31.c 
b/gcc/testsuite/gcc.target/riscv/predef-31.c
new file mode 100644
index ..4ea11442f995
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-31.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcb -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zca)
+#error "__riscv_zca"
+#endif
+
+#if !defined(__riscv_zcb)
+#error "__riscv_zcb"
+#endif
+
+  return 0;
+}
-- 
2.41.0

[PATCH v2 0/3] RISC-V: Add stub support for existing extensions

[Tsukasa OI via Gcc-patches]

PATCH v1:



Changes: v1 -> v2 (only in PATCH 3/3)
==

Removed: 'Zvkn' -> 'Zvknha' implication (not to cause test failure)
Added:   'Zfa' -> 'F' implication (just I forgot to add in PATCH v1)


Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add stub support for existing extensions (privileged)
  RISC-V: Add stub support for existing extensions (vendor)
  RISC-V: Add stub support for existing extensions (unprivileged)

 gcc/common/config/riscv/riscv-common.cc| 44 ++
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 +
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 +
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 +++
 4 files changed, 137 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c


base-commit: 614052dd4ea083e086712809c754ffebd9361316
-- 
2.41.0

[PATCH 2/2] RISC-V: Constant FP Optimization with 'Zfa'

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This commit implements an optimization for assignments from a FP constant
to a FP register using a FLI instruction from the 'Zfa' extension.

To this purpose, it adds the constraint "H" and adds hardfloat move
instructions a "H -> f" variant.  Because FLI instruction constraint is
a bit complex, it adds the riscv_get_float_fli_const function to parse
a floating point constant if appropriate and the validness is contained
in its return value.

It also modifies the cost model for floating point constants and implements
simple yet bit-accurate printer for valid finite FLI constants.

This optimization is partially based on AArch64
(vmov instruction handling).

gcc/ChangeLog:

* config/riscv/constraints.md (H): New.
* config/riscv/riscv-protos.h (enum riscv_float_fli_const_type):
New to identify the FLI constant type.
(struct riscv_float_fli_const): New to represent an optional
FLI constant.
* config/riscv/riscv.cc (riscv_get_float_fli_const): New function
to parse a CONST_DOUBLE and return optionally-valid FLI constant.
(riscv_const_insns): Modify CONST_DOUBLE cost model.
(riscv_output_move): Add FLI instruction outputs.
(riscv_print_operand): Print a finite FLI constant as a hexadecimal
FP representation or a string operand "min", "inf" or "nan".
* config/riscv/riscv.md (movhf_hardfloat, movsf_hardfloat,
movdf_hardfloat_rv32, movdf_hardfloat_rv64): Add "H" variant
for 'Zfa' extension-based FP constant moves.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zfa-fli-1.c: New test.
* gcc.target/riscv/zfa-fli-2.c: Ditto.
* gcc.target/riscv/zfa-fli-3.c: Ditto.
* gcc.target/riscv/zfa-fli-4.c: Ditto.
* gcc.target/riscv/zfa-fli-5.c: Ditto.
* gcc.target/riscv/zfa-fli-6.c: Ditto.
* gcc.target/riscv/zfa-fli-7.c: Ditto.
* gcc.target/riscv/zfa-fli-8.c: Ditto.
---
 gcc/config/riscv/constraints.md|   7 +
 gcc/config/riscv/riscv-protos.h|  34 +++
 gcc/config/riscv/riscv.cc  | 250 -
 gcc/config/riscv/riscv.md  |  24 +-
 gcc/testsuite/gcc.target/riscv/zfa-fli-1.c |  24 ++
 gcc/testsuite/gcc.target/riscv/zfa-fli-2.c |  24 ++
 gcc/testsuite/gcc.target/riscv/zfa-fli-3.c |  14 ++
 gcc/testsuite/gcc.target/riscv/zfa-fli-4.c | 111 +
 gcc/testsuite/gcc.target/riscv/zfa-fli-5.c |  98 
 gcc/testsuite/gcc.target/riscv/zfa-fli-6.c |  61 +
 gcc/testsuite/gcc.target/riscv/zfa-fli-7.c |  30 +++
 gcc/testsuite/gcc.target/riscv/zfa-fli-8.c |  39 
 12 files changed, 692 insertions(+), 24 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fli-8.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 44525b2da491..d57c72ef14f0 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -98,6 +98,13 @@
   (and (match_code "const_double")
(match_test "op == CONST0_RTX (mode)")))
 
+;; Floating-point constant that can be generated by a FLI instruction
+;; in the 'Zfa' standard extension.
+(define_constraint "H"
+  "@internal"
+  (and (match_code "const_double")
+   (match_test "riscv_get_float_fli_const (op).valid")))
+
 (define_memory_constraint "A"
   "An address that is held in a general-purpose register."
   (and (match_code "mem")
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 2fbed04ff84c..6effa2437251 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -80,6 +80,39 @@ struct riscv_address_info {
   enum riscv_symbol_type symbol_type;
 };
 
+/* Classifies a floating point constant possibly retrieved by
+   the FLI instructions.
+
+   RISCV_FLOAT_CONST_MIN
+   The minimum positive normal value for given mode.
+
+   RISCV_FLOAT_CONST_INF
+   Positive infinity.
+
+   RISCV_FLOAT_CONST_NAN
+   Canonical NaN (positive, quiet and zero payload NaN).
+
+   RISCV_FLOAT_CONST_FINITE
+   A finite number.  */
+enum riscv_float_fli_const_type {
+  RISCV_FLOAT_CONST_MIN,
+  RISCV_FLOAT_CONST_INF,
+  RISCV_FLOAT_CONST_NAN,
+  RISCV_FLOAT_CONST_FINITE,
+};
+
+/* Information about a floating point constant possibly retrieved by
+   the FLI instructions.  */
+struct riscv_float_fli_const {
+  bool valid: 1;
+  bool sign: 1;
+  enum riscv_float_fli_const_type type: 2;
+  /* Highest 2 bits of IEEE754 mantissa on RISCV_FLOAT_CONST_FINITE.  */
+  unsigned int 

[PATCH 1/2] RISC-V: Add support for the 'Zfa' extension

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This commit adds support for the 'Zfa' extension containing additional
floating point instructions, version 0.1 (stable and approved).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implication 'Zfa' -> 'F'.
(riscv_ext_version_table) Add support for the 'Zfa' extension.
(riscv_ext_flag_table) Set MASK_ZFA if 'Zfa' is available.
* config/riscv/riscv-opts.h (MASK_ZFA, TARGET_ZFA): New.
---
 gcc/common/config/riscv/riscv-common.cc | 3 +++
 gcc/config/riscv/riscv-opts.h   | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 21f83f26371f..01d68856bc40 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -121,6 +121,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvksg", "zvks"},
   {"zvksg", "zvkg"},
 
+  {"zfa", "f"},
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   {"zvfhmin", "zve32f"},
@@ -257,6 +258,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfa",   ISA_SPEC_CLASS_NONE, 0, 1},
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1400,6 +1402,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zvl32768b", _options::x_riscv_zvl_flags, MASK_ZVL32768B},
   {"zvl65536b", _options::x_riscv_zvl_flags, MASK_ZVL65536B},
 
+  {"zfa",   _options::x_riscv_zf_subext, MASK_ZFA},
   {"zfhmin",_options::x_riscv_zf_subext, MASK_ZFHMIN},
   {"zfh",   _options::x_riscv_zf_subext, MASK_ZFH},
   {"zvfhmin",   _options::x_riscv_zf_subext, MASK_ZVFHMIN},
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index aeea805b3425..e31ec7c4074a 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -249,11 +249,13 @@ enum riscv_entity
 #define MASK_ZFH  (1 << 1)
 #define MASK_ZVFHMIN  (1 << 2)
 #define MASK_ZVFH (1 << 3)
+#define MASK_ZFA  (1 << 4)
 
 #define TARGET_ZFHMIN  ((riscv_zf_subext & MASK_ZFHMIN) != 0)
 #define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
 #define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
 #define TARGET_ZVFH((riscv_zf_subext & MASK_ZVFH) != 0)
+#define TARGET_ZFA ((riscv_zf_subext & MASK_ZFA) != 0)
 
 #define MASK_ZMMUL  (1 << 0)
 #define TARGET_ZMMUL((riscv_zm_subext & MASK_ZMMUL) != 0)
-- 
2.41.0

[PATCH 0/2] RISC-V: Make "prefetch.i" built-in usable

[Tsukasa OI via Gcc-patches]

Hello,

and... I think this might be my first *large* patch set for GCC
contribution and definitely the first one to touch the machine description.

So, please review it carefully.


Background
===

This patch set adds an optimization to FP constant initialization using a
FLI instruction, which is a part of the 'Zfa' extension which provides
additional floating-point instructions.

FLI instructions ("fli.h" for binary16, "fli.s" for binary32, "fli.d" for
binary64 and "fli.q" for binary128 [which can be ignored because current
GCC for RISC-V does not natively support binary128]) provide an
load-immediate operation for following 32 immediates.

| Binary Encoding | Immediate (and its part of binary representation) |
| --- | --|
|`0` ( 0) | -1.0  (-0b1.00 * 2^(+ 0)) |
|`1` ( 1) | Minimum positive normal value |
| | sign=[0] exponent=[0..01] significand=[000..000]  |
|`00010` ( 2) | 1.00*2^(-16)  (+0b1.00 * 2^(-16)) |
|`00011` ( 3) | 1.00*2^(-15)  (+0b1.00 * 2^(-15)) |
|`00100` ( 4) | 1.00*2^(- 8)  (+0b1.00 * 2^(- 8)) |
|`00101` ( 5) | 1.00*2^(- 7)  (+0b1.00 * 2^(- 7)) |
|`00110` ( 6) | 1.00*2^(- 4)  (+0b1.00 * 2^(- 4)) = 0.0625|
|`00111` ( 7) | 1.00*2^(- 3)  (+0b1.00 * 2^(- 3)) = 0.125 |
|`01000` ( 8) | 1.00*2^(- 2)  (+0b1.00 * 2^(- 2)) : 0.25  |
|`01001` ( 9) | 1.25*2^(- 2)  (+0b1.01 * 2^(- 2)) : 0.3125|
|`01010` (10) | 1.50*2^(- 2)  (+0b1.10 * 2^(- 2)) : 0.375 |
|`01011` (11) | 1.75*2^(- 2)  (+0b1.11 * 2^(- 2)) : 0.4375|
|`01100` (12) | 1.00*2^(- 1)  (+0b1.00 * 2^(- 1)) : 0.5   |
|`01101` (13) | 1.25*2^(- 1)  (+0b1.01 * 2^(- 1)) : 0.625 |
|`01110` (14) | 1.50*2^(- 1)  (+0b1.10 * 2^(- 1)) : 0.75  |
|`0` (15) | 1.75*2^(- 1)  (+0b1.11 * 2^(- 1)) : 0.875 |
|`1` (16) | 1.00*2^(+ 0)  (+0b1.00 * 2^(+ 0)) : 1.0   |
|`10001` (17) | 1.25*2^(+ 0)  (+0b1.01 * 2^(+ 0)) : 1.25  |
|`10010` (18) | 1.50*2^(+ 0)  (+0b1.10 * 2^(+ 0)) : 1.5   |
|`10011` (19) | 1.75*2^(+ 0)  (+0b1.11 * 2^(+ 0)) : 1.75  |
|`10100` (20) | 1.00*2^(+ 1)  (+0b1.00 * 2^(+ 1)) : 2.0   |
|`10101` (21) | 1.25*2^(+ 1)  (+0b1.01 * 2^(+ 1)) : 2.5   |
|`10110` (22) | 1.50*2^(+ 1)  (+0b1.10 * 2^(+ 1)) : 3.0   |
|`10111` (23) | 1.00*2^(+ 2)  (+0b1.00 * 2^(+ 2)) = 4 |
|`11000` (24) | 1.00*2^(+ 3)  (+0b1.00 * 2^(+ 3)) = 8 |
|`11001` (25) | 1.00*2^(+ 4)  (+0b1.00 * 2^(+ 4)) = 16|
|`11010` (26) | 1.00*2^(+ 7)  (+0b1.00 * 2^(+ 7)) = 128   |
|`11011` (27) | 1.00*2^(+ 8)  (+0b1.00 * 2^(+ 8)) = 256   |
|`11100` (28) | 1.00*2^(+15)  (+0b1.00 * 2^(+15)) = 32768 |
|`11101` (29) | 1.00*2^(+16)  (+0b1.00 * 2^(+16)) = 65536 |
| | On "fli.h", this is equivalent to positive inf.   |
|`0` (30) | Positive infinity |
| | sign=[0] exponent=[1..11] significand=[000..000]  |
|`1` (31) | Canonical NaN (positive, quiet and zero payload)  |
| | sign=[0] exponent=[1..11] significand=[100..000]  |

Currently, initializing a FP constant (except zero) involves memory and its
use can be reduced by FLI instructions.

We may have a room to generate much complex constants with multiple FLI
instructions (e.g. like long integer constants) but for starter, we can
begin with optimizing one FP constant initialization with one FLI
instruction (and because FP arithmetic often requires larger latency,
benefits of making multiple FLI sequence is not high compared to integers).


FLI FP constant checking
=

An instruction with a similar role to RISC-V's FLI instructions is the Arm/
AArch64's vmov.f32 instruction. It provides a load-immediate operation for
constant that can be represented in the following form:

> (-1)^s * 0b1. * 2^r   (where -3 <= r <= +4; fits in 3-bits)

This patch is largely influenced by AArch64's handling but
compared to this, handling RISC-V's FLI FP constant can be a little tricky.

*   FLI normally generates only values with sign bit 0 except the binary
encoding 0 (which loads -1.0 with sign bit 1).
*   Not only finite values, FLI can generate positive infinity and
canonical NaN.
*   Because FLI can generate canonical NaN, handling NaN is preferred but
FLI only generates canonical NaN.  Since we can easily create a non-
canonical NaN with __builtin_nan ("[PAYLOAD]") and that could be a
direct return value of a function, we must reject non-canonical NaNs
(otherwise it'll generate "fli.d fa0,nan" where NaN is non-canonical).
*   Exponent range and mantissa constraint is a bit tricky.
On binary encodings 

[PATCH] RISC-V: Deduplicate #error messages in testsuite

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

"#error Feature macro not defined" is required to test the existence of an
extension through the preprocessor.  However, multiple occurrence of the
exact same error message will confuse the developer once an error is
encountered.

This commit replaces such error messages to
"#error Feature macro for `EXT' not defined" to make which
macro is missing.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zvkn.c: Deduplicate #error messages.
* gcc.target/riscv/zvkn-1.c: Ditto.
* gcc.target/riscv/zvknc.c: Ditto.
* gcc.target/riscv/zvknc-1.c: Ditto.
* gcc.target/riscv/zvknc-2.c: Ditto.
* gcc.target/riscv/zvkng.c: Ditto.
* gcc.target/riscv/zvkng-1.c: Ditto.
* gcc.target/riscv/zvkng-2.c: Ditto.
* gcc.target/riscv/zvks.c: Ditto.
* gcc.target/riscv/zvks-1.c: Ditto.
* gcc.target/riscv/zvksc.c: Ditto.
* gcc.target/riscv/zvksc-1.c: Ditto.
* gcc.target/riscv/zvksc-2.c: Ditto.
* gcc.target/riscv/zvksg.c: Ditto.
* gcc.target/riscv/zvksg-1.c: Ditto.
* gcc.target/riscv/zvksg-2.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/zvkn-1.c  | 10 +-
 gcc/testsuite/gcc.target/riscv/zvkn.c| 10 +-
 gcc/testsuite/gcc.target/riscv/zvknc-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvknc-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvknc.c   | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvkng-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvkng-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvkng.c   | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvks-1.c  | 10 +-
 gcc/testsuite/gcc.target/riscv/zvks.c| 10 +-
 gcc/testsuite/gcc.target/riscv/zvksc-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksc-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksc.c   | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksg-1.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksg-2.c | 14 +++---
 gcc/testsuite/gcc.target/riscv/zvksg.c   | 14 +++---
 16 files changed, 104 insertions(+), 104 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/zvkn-1.c 
b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
index 83935b068320..84a3b577a496 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn-1.c
@@ -3,23 +3,23 @@
 /* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt" { target { rv32 } } } 
*/
 
 #ifndef __riscv_zvkn
-#error Feature macro not defined
+#error Feature macro for `Zvkn' not defined
 #endif
 
 #ifndef __riscv_zvkned
-#error Feature macro not defined
+#error Feature macro for `Zvkned' not defined
 #endif
 
 #ifndef __riscv_zvknhb
-#error Feature macro not defined
+#error Feature macro for `Zvknhb' not defined
 #endif
 
 #ifndef __riscv_zvbb
-#error Feature macro not defined
+#error Feature macro for `Zvbb' not defined
 #endif
 
 #ifndef __riscv_zvkt
-#error Feature macro not defined
+#error Feature macro for `Zvkt' not defined
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/zvkn.c 
b/gcc/testsuite/gcc.target/riscv/zvkn.c
index af3db40c8f68..b42c1881b628 100644
--- a/gcc/testsuite/gcc.target/riscv/zvkn.c
+++ b/gcc/testsuite/gcc.target/riscv/zvkn.c
@@ -3,23 +3,23 @@
 /* { dg-options "-march=rv32gc_zvkn" { target { rv32 } } } */
 
 #ifndef __riscv_zvkn
-#error Feature macro not defined
+#error Feature macro for `Zvkn' not defined
 #endif
 
 #ifndef __riscv_zvkned
-#error Feature macro not defined
+#error Feature macro for `Zvkned' not defined
 #endif
 
 #ifndef __riscv_zvknhb
-#error Feature macro not defined
+#error Feature macro for `Zvknhb' not defined
 #endif
 
 #ifndef __riscv_zvbb
-#error Feature macro not defined
+#error Feature macro for `Zvbb' not defined
 #endif
 
 #ifndef __riscv_zvkt
-#error Feature macro not defined
+#error Feature macro for `Zvkt' not defined
 #endif
 
 int
diff --git a/gcc/testsuite/gcc.target/riscv/zvknc-1.c 
b/gcc/testsuite/gcc.target/riscv/zvknc-1.c
index eca276708954..5c456a6add78 100644
--- a/gcc/testsuite/gcc.target/riscv/zvknc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/zvknc-1.c
@@ -3,31 +3,31 @@
 /* { dg-options "-march=rv32gc_zvkned_zvknhb_zvbb_zvkt_zvbc" { target { rv32 } 
} } */
 
 #ifndef __riscv_zvknc
-#error Feature macro not defined
+#error Feature macro for `Zvknc' not defined
 #endif
 
 #ifndef __riscv_zvkn
-#error Feature macro not defined
+#error Feature macro for `Zvkn' not defined
 #endif
 
 #ifndef __riscv_zvkned
-#error Feature macro not defined
+#error Feature macro for `Zvkned' not defined
 #endif
 
 #ifndef __riscv_zvknhb
-#error Feature macro not defined
+#error Feature macro for `Zvknhb' not defined
 #endif
 
 #ifndef __riscv_zvbb
-#error Feature macro not defined
+#error Feature macro for `Zvbb' not defined
 #endif
 
 #ifndef __riscv_zvkt
-#error Feature macro not defined
+#error Feature macro for `Zvkt' not defined
 #endif
 
 #ifndef __riscv_zvbc
-#error Feature macro not 

[PATCH 2/3] RISC-V: Add stub support for existing extensions (vendor)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

This commit adds stub supported vendor extensions to
riscv_ext_version_table (no riscv_implied_info entries to add; all
information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_ext_version_table):
Add stub support for all vendor extensions supported by Binutils.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-30.c: New test for a stub
vendor extension 'XVentanaCondOps'.
---
 gcc/common/config/riscv/riscv-common.cc|  2 ++
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 ++
 2 files changed, 29 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 91b0316acfea..0c351105e015 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -298,6 +298,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
diff --git a/gcc/testsuite/gcc.target/riscv/predef-30.c 
b/gcc/testsuite/gcc.target/riscv/predef-30.c
new file mode 100644
index ..9784b9ce5033
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-30.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_xventanacondops -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_xventanacondops)
+#error "__riscv_xventanacondops"
+#endif
+
+  return 0;
+}
-- 
2.41.0

[PATCH 3/3] RISC-V: Add stub support for existing extensions (unprivileged)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

This commit adds stub supported standard unprivileged extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c except not yet
merged 'Zce', 'Zcmp' and 'Zcmt' support).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implications from unprivileged extensions.
(riscv_ext_version_table): Add stub support for all unprivileged
extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-31.c: New test for a stub unprivileged
extension 'Zcb' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc| 25 +
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 ++
 2 files changed, 56 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 0c351105e015..112bb86bd675 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -105,6 +105,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvl65536b", "zvl32768b"},
 
   {"zvkn", "zvkned"},
+  {"zvkn", "zvknha"},
   {"zvkn", "zvknhb"},
   {"zvkn", "zvbb"},
   {"zvkn", "zvkt"},
@@ -121,6 +122,19 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zvksg", "zvks"},
   {"zvksg", "zvkg"},
 
+  {"zcb", "zca"},
+  {"zcd", "zca"},
+  {"zcd", "d"},
+  {"zcf", "zca"},
+  {"zcf", "f"},
+  {"zce", "zca"},
+  {"zce", "zcb"},
+  {"zce", "zcmp"},
+  {"zce", "zcmt"},
+  {"zcmp", "zca"},
+  {"zcmt", "zca"},
+  {"zcmt", "zcicsr"},
+
   {"zfh", "zfhmin"},
   {"zfhmin", "f"},
   {"zvfhmin", "zve32f"},
@@ -197,6 +211,14 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zca",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zce",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcf",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -219,6 +241,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
 
   {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -265,6 +288,8 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zfa",   ISA_SPEC_CLASS_NONE, 0, 1},
+
   {"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
   {"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-31.c 
b/gcc/testsuite/gcc.target/riscv/predef-31.c
new file mode 100644
index ..4ea11442f995
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-31.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcb -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zca)
+#error "__riscv_zca"
+#endif
+
+#if !defined(__riscv_zcb)
+#error "__riscv_zcb"
+#endif
+
+  return 0;
+}
-- 
2.41.0

[PATCH 1/3] RISC-V: Add stub support for existing extensions (privileged)

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

As a start, this commit adds stub supported *privileged* extensions to
riscv_ext_version_table and its implications to riscv_implied_info
(all information is copied from Binutils' bfd/elfxx-riscv.c).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_implied_info): Add implications from privileged extensions.
(riscv_ext_version_table): Add stub support for all privileged
extensions supported by Binutils.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-29.c: New test for a stub privileged
extension 'Smstateen' with some implications.
---
 gcc/common/config/riscv/riscv-common.cc| 18 +++
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 ++
 2 files changed, 53 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 21f83f26371f..91b0316acfea 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -130,6 +130,14 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
 
+  {"smaia", "ssaia"},
+  {"smstateen", "ssstateen"},
+  {"smepmp", "zicsr"},
+  {"ssaia", "zicsr"},
+  {"sscofpmf", "zicsr"},
+  {"ssstateen", "zicsr"},
+  {"sstc", "zicsr"},
+
   {NULL, NULL}
 };
 
@@ -264,8 +272,18 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"smaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smepmp",ISA_SPEC_CLASS_NONE, 1, 0},
+  {"smstateen", ISA_SPEC_CLASS_NONE, 1, 0},
+
+  {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sscofpmf",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"ssstateen", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"sstc",  ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-29.c 
b/gcc/testsuite/gcc.target/riscv/predef-29.c
new file mode 100644
index ..61c6429be558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-29.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_smstateen -mabi=lp64 -mcmodel=medlow 
-misa-spec=20191213" } */
+
+int main () {
+
+#ifndef __riscv_arch_test
+#error "__riscv_arch_test"
+#endif
+
+#if __riscv_xlen != 64
+#error "__riscv_xlen"
+#endif
+
+#if !defined(__riscv_i) || (__riscv_i != (2 * 1000 * 1000 + 1 * 1000))
+#error "__riscv_i"
+#endif
+
+#if defined(__riscv_e)
+#error "__riscv_e"
+#endif
+
+#if !defined(__riscv_zicsr)
+#error "__riscv_zicsr"
+#endif
+
+#if !defined(__riscv_smstateen)
+#error "__riscv_smstateen"
+#endif
+
+#if !defined(__riscv_ssstateen)
+#error "__riscv_ssstateen"
+#endif
+
+  return 0;
+}
-- 
2.41.0

[PATCH 0/3] RISC-V: Add stub support for existing extensions

[Tsukasa OI via Gcc-patches]

Hello,

After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions, we have no
guarantee that we can share the same architectural string with Binutils
(specifically, the assembler).

To avoid compilation errors on shared Assembler-C/C++ projects, GCC should
support almost all extensions that Binutils support, even if the GCC does
not touch a thing.

In this patch set, it adds stub extension support along with its
implications (for GCC preprocessor support).

The author excluded those extensions:

1.  'Zicntr' and 'Zihpm'
(because additional compatibility measures are required)
2.  'Q' and "Zqinx"
(because GCC does not support 'Q' and 'Zqinx' is not ratified)

and included following extensions not yet supported by Binutils:

*   'Zcmp', 'Zcmt' and 'Zce' extensions
They are ratified and if we only need a stub support, it's relatively
easy to implement.

This patch set consists of three patches:

1.  Privileged Extensions
Unlikely to cause merge conflicts and easy to implement.
2.  Vendor Extension ('XVentanaCondOps')
Unlikely to cause merge conflicts unless someone tries to merge
optimization using 'Zicond' with 'XVentanaCondOps' (because 'Zicond' and
'XVentanaCondOps' are pretty much the same except encodings).
3.  Standard Unprivileged Extensions
Likely to cause merge conflicts depending on the order to apply patches.
In that case, prefer others (because this patchset adds *stub* support
for those extensions).

On this patch set, I focused on adding stub support for new extensions in
GCC (in the GCC perspective) and not all Binutils' contents are ported.

I'll submit separate patch set to port additional implications (e.g.
'M' -> 'Zmmul', 'Zve32x' -> 'Zicsr').

And despite that I implemented stub 'Zce' support, its implications are not
complete (e.g. 'Zce' + 'F' -> 'Zcf' is not implemented and planned for the
next patch set).

Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Add stub support for existing extensions (privileged)
  RISC-V: Add stub support for existing extensions (vendor)
  RISC-V: Add stub support for existing extensions (unprivileged)

 gcc/common/config/riscv/riscv-common.cc| 45 ++
 gcc/testsuite/gcc.target/riscv/predef-29.c | 35 +
 gcc/testsuite/gcc.target/riscv/predef-30.c | 27 +
 gcc/testsuite/gcc.target/riscv/predef-31.c | 31 +++
 4 files changed, 138 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-30.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-31.c


base-commit: 8be20733b38c200f375cacf698d6b85e76055bcd
-- 
2.41.0

Re: [RFC PATCH 0/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

On 2023/08/12 8:30, Jeff Law wrote:
> 
> 
> On 8/9/23 16:39, Tsukasa OI wrote:
>> On 2023/08/10 5:05, Jeff Law wrote:
> 
>>> I'd tend to think we do not want to expose the intrinsic unless the
>>> right extensions are enabled -- even though the encoding is a no-op and
>>> we could emit it as a .insn.
>>
>> I think that makes sense.  The only reason I implemented the
>> no-'Zihintpause' version is because GCC 13 implemented the built-in
>> unconditionally.  If the compatibility breakage is considered minimum (I
>> don't know, though), I'm ready to submit 'Zihintpause'-only version of
>> this patch set.
> While it's a compatibility break I don't think we have a need to
> preserve this kind of compatibility.  I suspect anyone using
> __builtin_riscv_pause was probably already turning on Zihintpause and if
> they weren't they should have been :-0
> 
> 
> I'm sure we'll kick this around in the Tuesday meeting and hopefully
> make a decision about the desired direction.  You're obviously welcome
> to join if you're inclined.  Let me know if you need an invite.
> 
> jeff
> 

I'll not be able to attend that meeting due to Japanese religious events
around Aug 13-16 (it may not be impossible but at least difficult) but
look forward seeing that some conclusion is made.

I leave two patch sets corresponding two options so in either case, we
can apply a fix after the conclusion is made.

(1) __builtin_riscv_pause for 'Zihintpause'-only

(2) __builtin_riscv_pause for all


Thanks,
Tsukasa

Re: [PATCH] RISC-V: Revive test case PR 102957

[Tsukasa OI via Gcc-patches]

On 2023/08/11 23:15, Jeff Law wrote:
> 
> 
> On 8/11/23 03:11, Tsukasa OI via Gcc-patches wrote:
>> From: Tsukasa OI 
>>
>> Commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
>> extensions") changed how do we handle unknown extensions and
>> commit 6f709f79c915a ("[committed] [RISC-V] Fix expected diagnostic
>> messages
>> in testsuite") "fixed" test failures caused by that change (on
>> pr102957.c,
>> by testing the error message after the first change).
>>
>> However, the latter change will break the original intent of PR 102957
>> test
>> case because we wanted to make sure that we can parse a valid two-letter
>> extension name.
>>
>> Fortunately, there is a valid two-letter extension name, 'Zk' (standard
>> scalar cryptography extension superset with NIST algorithm suite).
>>
>> This commit puts this extension name and revives the intent of the
>> test case
>> for PR 102957.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/pr102957.c: Remove "dg-error" because we don't
>> need to test for error message.  Use the 'Zk' extension to continue
>> testing whether we can use valid two-letter extensions.
> This doesn't look right to me.  The whole point of this specific dg line
> is to verify that we get an error with an invalid extension specification.
> 
> What might make more sense would be to split this into two tests.  One
> which continues to test that we get an error for something like zb and
> the other with everything else.
> 
> jeff
> 

Originally, it tested that a two letter extension ('Zb') is accepted by
GCC (because the background of PR 102957 was GCC assumed multi-letter
'Z' extensions are three letters or more).

After rejecting unrecognized extensions, "dg-error" is added **just to
avoid the test failure** and that doesn't look right.  Yes, we now don't
have an ICE (like in the original report) but after the PR 102957 fix,
we just accepted it, not rejecting it.

Instead, we have a valid (recognized) two-letter 'Z' extension: 'Zk'.  I
think replacing "zb" with "zk" is more correct considering the original
bug report (PR 102957) and its assumption.

cf. <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102957>

Regards,
Tsukasa

[PATCH] RISC-V: Revive test case PR 102957

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

Commit c283c4774d1c ("RISC-V: Throw compilation error for unknown
extensions") changed how do we handle unknown extensions and
commit 6f709f79c915a ("[committed] [RISC-V] Fix expected diagnostic messages
in testsuite") "fixed" test failures caused by that change (on pr102957.c,
by testing the error message after the first change).

However, the latter change will break the original intent of PR 102957 test
case because we wanted to make sure that we can parse a valid two-letter
extension name.

Fortunately, there is a valid two-letter extension name, 'Zk' (standard
scalar cryptography extension superset with NIST algorithm suite).

This commit puts this extension name and revives the intent of the test case
for PR 102957.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/pr102957.c: Remove "dg-error" because we don't
need to test for error message.  Use the 'Zk' extension to continue
testing whether we can use valid two-letter extensions.
---
 gcc/testsuite/gcc.target/riscv/pr102957.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/pr102957.c 
b/gcc/testsuite/gcc.target/riscv/pr102957.c
index 5273ee6c5018..fe6241466354 100644
--- a/gcc/testsuite/gcc.target/riscv/pr102957.c
+++ b/gcc/testsuite/gcc.target/riscv/pr102957.c
@@ -1,7 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gzb -mabi=lp64" } */
+/* { dg-options "-march=rv64gzk -mabi=lp64" } */
 int foo()
 {
 }
-
-/* { dg-error "extension 'zb' starts with 'z' but is unsupported standard 
extension" "" { target *-*-* } 0 } */

base-commit: bcda361daaec8623c91d0dff3ea8e576373b5f50
-- 
2.41.0

[PATCH 1/1] RISC-V: Make "prefetch.i" built-in usable

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

The "__builtin_riscv_zicbop_cbo_prefetchi" built-in function was terribly
broken so that practically unusable.  It emitted "prefetch.i" but with no
meaningful arguments.

Though incompatible, this commit completely changes the function prototype
of this built-in and makes it usable.  To minimize the functionality issues,
it renames the built-in to "__builtin_riscv_zicbop_prefetch_i".

gcc/ChangeLog:

* config/riscv/riscv-cmo.def: Fix function prototype.
* config/riscv/riscv.md (riscv_prefetchi_): Fix instruction
prototype.  Remove possible prefectch type argument
* doc/extend.texi: Document __builtin_riscv_zicbop_prefetch_i.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/cmo-zicbop-1.c: Reflect new built-in prototype.
* gcc.target/riscv/cmo-zicbop-2.c: Likewise.
---
 gcc/config/riscv/riscv-cmo.def|  4 ++--
 gcc/config/riscv/riscv.md |  5 ++---
 gcc/doc/extend.texi   |  7 +++
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c |  8 +---
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 10 ++
 5 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def
index b92044dc6ff9..2286c8a25544 100644
--- a/gcc/config/riscv/riscv-cmo.def
+++ b/gcc/config/riscv/riscv-cmo.def
@@ -13,8 +13,8 @@ RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", 
RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV
 RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE_VOID_PTR, zero64),
 
 // zicbop
-RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_SI_FTYPE_SI, prefetchi32),
-RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, 
RISCV_DI_FTYPE_DI, prefetchi64),
+RISCV_BUILTIN (prefetchi_si, "zicbop_prefetch_i", 
RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, prefetchi32),
+RISCV_BUILTIN (prefetchi_di, "zicbop_prefetch_i", 
RISCV_BUILTIN_DIRECT_NO_TARGET, RISCV_VOID_FTYPE_VOID_PTR, prefetchi64),
 
 // zbkc or zbc
 RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, 
clmul_zbkc32_or_zbc32),
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 688fd697255b..5658c7b7e113 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3273,9 +3273,8 @@
 })
 
 (define_insn "riscv_prefetchi_"
-  [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
-  (match_operand:X 1 "imm5_operand" "i")]
-  UNSPECV_PREI)]
+  [(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")]
+UNSPECV_PREI)]
   "TARGET_ZICBOP"
   "prefetch.i\t%a0"
 )
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 89c5b4ea2b20..0eb98fc89e3f 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21575,6 +21575,13 @@ Xgnuzihintpausestate extension, which redefines the 
@code{pause} instruction to
 change architectural state.
 @enddefbuiltin
 
+@defbuiltin{void __builtin_riscv_zicbop_prefetch_i (void *@var{addr})}
+Generates the @code{prefetch.i} machine instruction to instruct the hardware
+that a cache block containing @var{addr} is likely to be accessed by an
+instruction fetch in the near future.
+Available if the Zicbop extension is enabled.
+@enddefbuiltin
+
 @node RISC-V Vector Intrinsics
 @subsection RISC-V Vector Intrinsics
 
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
index c5d78c1763d3..0d5b58c4fadf 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c
@@ -13,11 +13,13 @@ void foo (char *p)
   __builtin_prefetch (p, 1, 3);
 }
 
-int foo1()
+void foo1 ()
 {
-  return __builtin_riscv_zicbop_cbo_prefetchi(1);
+  __builtin_riscv_zicbop_prefetch_i(0);
+  __builtin_riscv_zicbop_prefetch_i();
+  __builtin_riscv_zicbop_prefetch_i((void*)0x111);
 }
 
-/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.i" 3 } } */
 /* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
 /* { dg-final { scan-assembler-times "prefetch.w" 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c 
b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
index 6576365b39ca..09655c4b8593 100644
--- a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
+++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c
@@ -13,11 +13,13 @@ void foo (char *p)
   __builtin_prefetch (p, 1, 3);
 }
 
-int foo1()
+void foo1 ()
 {
-  return __builtin_riscv_zicbop_cbo_prefetchi(1);
+  __builtin_riscv_zicbop_prefetch_i(0);
+  __builtin_riscv_zicbop_prefetch_i();
+  __builtin_riscv_zicbop_prefetch_i((void*)0x111);
 }
 
-/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */
+/* { dg-final { scan-assembler-times "prefetch.i" 3 } } */
 /* { dg-final { scan-assembler-times "prefetch.r" 4 } } */
-/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ 
+/* { 

[PATCH 0/1] RISC-V: Make "prefetch.i" built-in usable

[Tsukasa OI via Gcc-patches]

Hello,

I found that a built-in function "__builtin_riscv_zicbop_cbo_prefetchi" is
terribly broken so that this is practically unusable.  It emits the
"prefetch.i" machine instruction HINT but with no usable arguments.

Contents of a.c:

> void function_to_be_called(void);
> 
> void sample(void)
> {
> __builtin_riscv_zicbop_cbo_prefetchi(_to_be_called);
> function_to_be_called();
> }


Compiling with the 'Zicbop' extension fails.

> $ riscv64-unknown-elf-gcc -O2 -march=rv64i_zicbop -mabi=lp64 -c a.c
> a.c: In function 'sample':
> a.c:5:42: warning: passing argument 1 of 
> '__builtin_riscv_zicbop_cbo_prefetchi' makes integer from pointer without a 
> cast [-Wint-conversion]
> 5 | __builtin_riscv_zicbop_cbo_prefetchi(_to_be_called);
>   |  ^~
>   |  |
>   |  void (*)(void)
> a.c:5:42: note: expected 'long int' but argument is of type 'void (*)(void)'
> a.c:5:5: error: invalid argument to built-in function
> 5 | __builtin_riscv_zicbop_cbo_prefetchi(_to_be_called);
>   | ^~~~

seems the prototype of this built-in function is...

> int  __builtin_riscv_zicbop_cbo_prefetchi(int);  // RV32
> long __builtin_riscv_zicbop_cbo_prefetchi(long); // RV64

I started to have a bad feeling about this.




Looking at the test case, following code compiles (sort of).

> void sample(void)
> {
> __builtin_riscv_zicbop_cbo_prefetchi(1); /* integer constant: 0-4 
> (inclusive) */
> }

WHAT IS THIS PREFETCHING!?

The answer was obvious (tested with GCC 13.2.0).

> $ riscv64-unknown-elf-gcc -O2 -march=rv64i_zicbop -mabi=lp64 -S a.c
> $ cat a.s
> .file   "a.c"
> .option nopic
> .attribute arch, "rv64i2p1_zicbop1p0"
> .attribute unaligned_access, 0
> .attribute stack_align, 16
> .text
> .align  2
> .globl  sample
> .type   sample, @function
> sample:
> li  a5,0
> prefetch.i  0(a5)
> ret
> .size   sample, .-sample
> .ident  "GCC: (gc891d8dc23e1) 13.2.0"

... none (NULL).  Even the prefetching constant (1) is ignored.




It makes no sense whatsoever.  This patch set is definitely compatibility-
breaking but necessary to make "prefetch.i" work.

This patch set makes following built-in function.

> void  __builtin_riscv_zicbop_prefetch_i(void*);

Did you notice that I renamed the function?  There are three reasons:

1.  We needed to break the compatibility anyway.
2.  To avoid functionality problems.
Co-existing functional and non-functional
__builtin_riscv_zicbop_cbo_prefetchi built-in felt like a nightmare.
3.  Although this is also a cache block operation, the instruction
"prefetch.i" does not have the name "cbo" in it
(unlike "__builtin_riscv_zicbom_cbo_clean" corresponding "cbo.clean").


Let's make a working sample (a.c):

> void function_to_be_called(void);
> 
> void sample(void)
> {
> __builtin_riscv_zicbop_prefetch_i(_to_be_called);
> function_to_be_called();
> }

And take look at the output assembly and its relocations.

> $ riscv64-unknown-elf-gcc -O2 -march=rv64i_zicbop -mabi=lp64 -S a.c
> $ cat a.s
> .file   "a.c"
> .option nopic
> .attribute arch, "rv64i2p1_zicbop1p0"
> .attribute unaligned_access, 0
> .attribute stack_align, 16
> .text
> .align  2
> .globl  sample
> .type   sample, @function
> sample:
> lui a5,%hi(function_to_be_called)
> addia5,a5,%lo(function_to_be_called)
> prefetch.i  0(a5)
> tailfunction_to_be_called
> .size   sample, .-sample
> .ident  "GCC: (GNU) 14.0.0 20230810 (experimental)"



I hope this issue is fixed soon.

Sincerely,
Tsukasa




Tsukasa OI (1):
  RISC-V: Make "prefetch.i" built-in usable

 gcc/config/riscv/riscv-cmo.def|  4 ++--
 gcc/config/riscv/riscv.md |  5 ++---
 gcc/doc/extend.texi   |  7 +++
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c |  8 +---
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 10 ++
 5 files changed, 22 insertions(+), 12 deletions(-)


base-commit: 9b099a83b45b8fcdfc07d518e05d36ea741b2227
-- 
2.41.0

[RFC PATCH 0/2] RISC-V: Make __builtin_riscv_pause 'Zihintpause' only

[Tsukasa OI via Gcc-patches]

**WARNING**

Following patch sets are exclusive:

1.  [RFC PATCH v2] RISC-V: __builtin_riscv_pause for all environment
2.  [RFC PATCH] RISC-V: Make __builtin_riscv_pause 'Zihintpause' only (this)

See 
for the background of this patch set.


Changes: (all environment) v1 -> ('Zihintpause'-only) v1

*   Based on the feedback from Jeff Law, I made an alternative patch set
which makes "__builtin_riscv_pause" 'Zihintpause'-only.


Comparison: Patch sets [1] and [2] (this)

*   [1] completely preserves the compatibility with GCC 13
([2] removes __builtin_riscv_pause if the 'Zihintpause' extension is
 absent, making a minor compatibility issue)
*   Because of the nature of the instrinsic, [2] is more natural
("pause" is defined in the 'Zihintpause' extension).


Please consider those patch sets and decide which to apply.

Sincerely,
Tsukasa




Tsukasa OI (2):
  RISC-V: Make __builtin_riscv_pause 'Zihintpause' only
  RISC-V: Fix documentation of __builtin_riscv_pause

 gcc/common/config/riscv/riscv-common.cc|  2 ++
 gcc/config/riscv/riscv-builtins.cc |  4 ++--
 gcc/config/riscv/riscv-opts.h  |  2 ++
 gcc/config/riscv/riscv.md  |  2 +-
 gcc/doc/extend.texi|  6 +++---
 gcc/testsuite/gcc.target/riscv/builtin_pause.c | 10 --
 gcc/testsuite/gcc.target/riscv/zihintpause-1.c | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause-2.c | 11 +++
 8 files changed, 32 insertions(+), 16 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-2.c


base-commit: 9b099a83b45b8fcdfc07d518e05d36ea741b2227
-- 
2.41.0

[RFC PATCH 2/2] RISC-V: Fix documentation of __builtin_riscv_pause

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This built-in does not imply the 'Xgnuzihintpausestate' extension.
It does not change architectural state (because all HINTs are prohibited
from doing that).

gcc/ChangeLog:

* doc/extend.texi: Fix the description of __builtin_riscv_pause.
---
 gcc/doc/extend.texi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 89c5b4ea2b20..7be27430666a 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21570,9 +21570,9 @@ Returns the value that is currently set in the 
@samp{tp} register.
 @enddefbuiltin
 
 @defbuiltin{void __builtin_riscv_pause (void)}
-Generates the @code{pause} (hint) machine instruction.  This implies the
-Xgnuzihintpausestate extension, which redefines the @code{pause} instruction to
-change architectural state.
+Generates the @code{pause} (hint) machine instruction, indicating that the
+current hart should be temporarily paused or slowed down.
+Available if the Zihintpause extension is enabled.
 @enddefbuiltin
 
 @node RISC-V Vector Intrinsics
-- 
2.41.0

[RFC PATCH 1/2] RISC-V: Make __builtin_riscv_pause 'Zihintpause' only

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler).  However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zihintpause' extension disabled.

Despite that the "pause" instruction code (0x010f) is a HINT and
emitting its instruction code is safe in any environment, enabling the
built-in only for certain environment is not a good idea.

This commit implements handling for the 'Zihintpause' extension and makes
__built_riscv_pause built-in 'Zihintpause'-only.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_ext_version_table): Implement the 'Zihintpause' extension,
version 2.0.  (riscv_ext_flag_table) Add 'Zihintpause' handling.
* config/riscv/riscv-builtins.cc: Remove availability predicate
"always" and add "hint_pause", corresponding the existence of the
'Zihintpause' extension.
(riscv_builtins) Change che "riscv_pause" requirements.
* config/riscv/riscv-opts.h
(MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New.
* config/riscv/riscv.md (riscv_pause): Make it only available when
the 'Zihintpause' extension is enabled.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/builtin_pause.c: Removed.
* gcc.target/riscv/zihintpause-1.c:
New test when the 'Zihintpause' extension is enabled.
* gcc.target/riscv/zihintpause-2.c: Likewise.
---
 gcc/common/config/riscv/riscv-common.cc|  2 ++
 gcc/config/riscv/riscv-builtins.cc |  4 ++--
 gcc/config/riscv/riscv-opts.h  |  2 ++
 gcc/config/riscv/riscv.md  |  2 +-
 gcc/testsuite/gcc.target/riscv/builtin_pause.c | 10 --
 gcc/testsuite/gcc.target/riscv/zihintpause-1.c | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause-2.c | 11 +++
 7 files changed, 29 insertions(+), 13 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f25131eab28b..b77fdb909567 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -209,6 +209,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
 
   {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1343,6 +1344,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zkt",_options::x_riscv_zk_subext, MASK_ZKT},
 
   {"zihintntl", _options::x_riscv_zi_subext, MASK_ZIHINTNTL},
+  {"zihintpause", _options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
 
   {"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
   {"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 79681d759628..73e1512a5992 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -122,7 +122,7 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) 
&& !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
-AVAIL (always, (!0))
+AVAIL (hint_pause, TARGET_ZIHINTPAUSE)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -179,7 +179,7 @@ static const struct riscv_builtin_description 
riscv_builtins[] = {
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
-  DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, always),
+  DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, hint_pause),
 };
 
 /* Index I is the function declaration for riscv_builtins[I], or null if the
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 28d9b81bd800..a6c3e0c9098f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -102,10 +102,12 @@ enum riscv_entity
 #define MASK_ZICSR(1 << 0)
 #define MASK_ZIFENCEI (1 << 1)
 #define MASK_ZIHINTNTL (1 << 2)
+#define MASK_ZIHINTPAUSE (1 << 3)
 
 #define TARGET_ZICSR((riscv_zi_subext & MASK_ZICSR) != 0)
 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
 #define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
+#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
 
 #define MASK_ZAWRS   (1 << 0)
 #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 688fd697255b..44ea1c54b96b 100644
--- 

[RFC PATCH v2 1/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler).  However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zihintpause' extension disabled.

However, the "pause" instruction code (0x010f) is a HINT and emitting
its instruction code is safe in any environment.

This commit implements handling for the 'Zihintpause' extension and emits
".insn 0x010f" instead of "pause" only if the extension is disabled
(making the diagnostics better).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_ext_version_table): Implement the 'Zihintpause' extension,
version 2.0.  (riscv_ext_flag_table) Add 'Zihintpause' handling.
* config/riscv/riscv-builtins.cc: Remove availability predicate
"always" and add "hint_pause" and "hint_pause_pseudo", corresponding
the existence of the 'Zihintpause' extension.
(riscv_builtins) Split builtin implementation depending on the
existence of the 'Zihintpause' extension.
* config/riscv/riscv-opts.h
(MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New.
* config/riscv/riscv.md (riscv_pause): Make it only available when
the 'Zihintpause' extension is enabled.  (riscv_pause_insn) New
"pause" implementation when the 'Zihintpause' extension is disabled.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/builtin_pause.c: Removed.
* gcc.target/riscv/zihintpause-1.c:
New test when the 'Zihintpause' extension is enabled.
* gcc.target/riscv/zihintpause-2.c: Likewise.
* gcc.target/riscv/zihintpause-noarch.c:
New test when the 'Zihintpause' extension is disabled.
---
 gcc/common/config/riscv/riscv-common.cc |  2 ++
 gcc/config/riscv/riscv-builtins.cc  |  6 --
 gcc/config/riscv/riscv-opts.h   |  2 ++
 gcc/config/riscv/riscv.md   |  7 ++-
 gcc/testsuite/gcc.target/riscv/builtin_pause.c  | 10 --
 gcc/testsuite/gcc.target/riscv/zihintpause-1.c  | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause-2.c  | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c | 12 
 8 files changed, 48 insertions(+), 13 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index f25131eab28b..b77fdb909567 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -209,6 +209,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
 
   {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1343,6 +1344,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zkt",_options::x_riscv_zk_subext, MASK_ZKT},
 
   {"zihintntl", _options::x_riscv_zi_subext, MASK_ZIHINTNTL},
+  {"zihintpause", _options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
 
   {"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
   {"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 79681d759628..554fb7f69bb0 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -122,7 +122,8 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) 
&& !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
-AVAIL (always, (!0))
+AVAIL (hint_pause, TARGET_ZIHINTPAUSE)
+AVAIL (hint_pause_pseudo, !TARGET_ZIHINTPAUSE)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -179,7 +180,8 @@ static const struct riscv_builtin_description 
riscv_builtins[] = {
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
-  DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, always),
+  RISCV_BUILTIN (pause, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE, hint_pause),
+  RISCV_BUILTIN (pause_insn, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE, hint_pause_pseudo),
 };
 
 /* Index I is the function declaration for riscv_builtins[I], or null if the
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 28d9b81bd800..a6c3e0c9098f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h

[RFC PATCH v2 2/2] RISC-V: Fix documentation of __builtin_riscv_pause

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This built-in does not imply the 'Xgnuzihintpausestate' extension.
It does not change architectural state (because all HINTs are prohibited
from doing that).

gcc/ChangeLog:

* doc/extend.texi: Fix the description of __builtin_riscv_pause.
---
 gcc/doc/extend.texi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 89c5b4ea2b20..7ebbe70c78d6 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21570,9 +21570,9 @@ Returns the value that is currently set in the 
@samp{tp} register.
 @enddefbuiltin
 
 @defbuiltin{void __builtin_riscv_pause (void)}
-Generates the @code{pause} (hint) machine instruction.  This implies the
-Xgnuzihintpausestate extension, which redefines the @code{pause} instruction to
-change architectural state.
+Generates the @code{pause} (hint) machine instruction.  If the target 
implements
+the Zihintpause extension, it indicates that the current hart should be
+temporarily paused or slowed down.
 @enddefbuiltin
 
 @node RISC-V Vector Intrinsics
-- 
2.41.0

[RFC PATCH v2 0/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

**WARNING**

Following patch sets are exclusive:

1.  [RFC PATCH v2] RISC-V: __builtin_riscv_pause for all environment (this)
2.  [RFC PATCH] RISC-V: Make __builtin_riscv_pause 'Zihintpause' only

See 
for the background of this patch set.


Changes: v1 -> v2

*   Improve test case to test both RV32 and RV64 (+'Zihintpause').


Comparison: Patch sets [1] (this) and [2]

*   [1] completely preserves the compatibility with GCC 13
([2] removes __builtin_riscv_pause if the 'Zihintpause' extension is
 absent, making a minor compatibility issue)
*   Because of the nature of the instrinsic, [2] is more natural
("pause" is defined in the 'Zihintpause' extension).


Please consider those patch sets and decide which to apply.

Sincerely,
Tsukasa




Tsukasa OI (2):
  RISC-V: __builtin_riscv_pause for all environment
  RISC-V: Fix documentation of __builtin_riscv_pause

 gcc/common/config/riscv/riscv-common.cc |  2 ++
 gcc/config/riscv/riscv-builtins.cc  |  6 --
 gcc/config/riscv/riscv-opts.h   |  2 ++
 gcc/config/riscv/riscv.md   |  7 ++-
 gcc/doc/extend.texi |  6 +++---
 gcc/testsuite/gcc.target/riscv/builtin_pause.c  | 10 --
 gcc/testsuite/gcc.target/riscv/zihintpause-1.c  | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause-2.c  | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c | 12 
 9 files changed, 51 insertions(+), 16 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c


base-commit: 9b099a83b45b8fcdfc07d518e05d36ea741b2227
-- 
2.41.0

Re: [RFC PATCH 0/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

On 2023/08/10 5:05, Jeff Law wrote:
> 
> 
> On 8/9/23 00:11, Tsukasa OI via Gcc-patches wrote:
>> Hello,
>>
>> I found that a built-in function "__builtin_riscv_pause" is not usable
>> unless we enable the 'Zihintpause' extension explicitly (still, this
>> built-in exists EVEN IF the 'Zihintpause' extension is disabled).
>>
>> Contents of a.c:
>>
>>> void sample(void)
>>> {
>>>  __builtin_riscv_pause();
>>> }
>>
>>
>> Compiling with the 'Zihintpause' extension is fine.
>>
>>> $ riscv64-unknown-elf-gcc -O2 -march=rv64i_zihintpause -mabi=lp64 -c a.c
>>
>>
>> However, compiling without the 'Zihintpause' causes an assembler error
>> (tested with GNU Binutils 2.41):
>>
>>> $ riscv64-unknown-elf-gcc -O2 -march=rv64i -mabi=lp64 -c a.c
>>> /tmp/ccFjacAz.s: Assembler messages:
>>> /tmp/ccFjacAz.s:11: Error: unrecognized opcode `pause', extension
>>> `zihintpause' required
>>
>>
>> This is because:
>>
>> 1.  GCC does not handle the 'Zihintpause' extension and
>> 2.  "riscv_pause" (insn) unconditionally emits "pause" even if the
>>  assembler does not accept it (when the extension is disabled).
>>
>>
>> This patch set (PATCH 1/2) resolves this issue by:
>>
>> 1.  Handling the 'Zihintpause' extension and
>> 2.  Splitting the "__builtin_riscv_pause" implementation
>>  depending on the existence of the 'Zihintpause' extension.
>>
>> Because a released version of GCC defines "__builtin_riscv_pause"
>> unconditionally, I chose to define no-'Zihintpause' version.
>>
>> There is another option to unconditionally emit ".insn 0x010f"
>> (the machine code of "pause") but I didn't because I wanted to improve
>> the
>> diagnostics (e.g. *.s output).
>>
>> I also fixed the description of this built-in function (in PATCH 2/2).
>>
>>
>> I'm not sure whether this is a good method to split the implementation
>> depending on the 'Zihintpause' extension.  Other than that, I believe
>> that
>> this is okay and approval is appreciated.
>>
>> Note that because I assigned copyright of GCC contribution to FSF, I
>> didn't
>> attach "Signed-off-by" tag.  Tell me if I need it.
> I'd tend to think we do not want to expose the intrinsic unless the
> right extensions are enabled -- even though the encoding is a no-op and
> we could emit it as a .insn.

I think that makes sense.  The only reason I implemented the
no-'Zihintpause' version is because GCC 13 implemented the built-in
unconditionally.  If the compatibility breakage is considered minimum (I
don't know, though), I'm ready to submit 'Zihintpause'-only version of
this patch set.

Thanks,
Tsukasa

> 
> If others think otherwise, I'll go with the consensus opinion.  So let's
> hold off a bit until others have chimed in.
> 
> Thanks,
> jeff
> 

[RFC PATCH 2/2] RISC-V: Fix documentation of __builtin_riscv_pause

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

This built-in does not imply the 'Xgnuzihintpausestate' extension.
It does not change architectural state (because all HINTs are prohibited
from doing that).

gcc/ChangeLog:

* doc/extend.texi: Fix the description of __builtin_riscv_pause.
---
 gcc/doc/extend.texi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 89c5b4ea2b20..7ebbe70c78d6 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21570,9 +21570,9 @@ Returns the value that is currently set in the 
@samp{tp} register.
 @enddefbuiltin
 
 @defbuiltin{void __builtin_riscv_pause (void)}
-Generates the @code{pause} (hint) machine instruction.  This implies the
-Xgnuzihintpausestate extension, which redefines the @code{pause} instruction to
-change architectural state.
+Generates the @code{pause} (hint) machine instruction.  If the target 
implements
+the Zihintpause extension, it indicates that the current hart should be
+temporarily paused or slowed down.
 @enddefbuiltin
 
 @node RISC-V Vector Intrinsics
-- 
2.41.0

[RFC PATCH 1/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

The "pause" RISC-V hint instruction requires the 'Zihintpause' extension
(in the assembler).  However, GCC emits "pause" unconditionally, making
an assembler error while compiling code with __builtin_riscv_pause while
the 'Zihintpause' extension disabled.

However, the "pause" instruction code (0x010f) is a HINT and emitting
its instruction code is safe in any environment.

This commit implements handling for the 'Zihintpause' extension and emits
".insn 0x010f" instead of "pause" only if the extension is disabled
(making the diagnostics better).

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc
(riscv_ext_version_table): Implement the 'Zihintpause' extension,
version 2.0.  (riscv_ext_flag_table) Add 'Zihintpause' handling.
* config/riscv/riscv-builtins.cc: Remove availability predicate
"always" and add "hint_pause" and "hint_pause_pseudo", corresponding
the existence of the 'Zihintpause' extension.
(riscv_builtins) Split builtin implementation depending on the
existence of the 'Zihintpause' extension.
* config/riscv/riscv-opts.h
(MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New.
* config/riscv/riscv.md (riscv_pause): Make it only available when
the 'Zihintpause' extension is enabled.  (riscv_pause_insn) New
"pause" implementation when the 'Zihintpause' extension is disabled.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/builtin_pause.c: Removed.
* gcc.target/riscv/zihintpause.c:
New test when the 'Zihintpause' extension is enabled.
* gcc.target/riscv/zihintpause-noarch.c:
New test when the 'Zihintpause' extension is disabled.
---
 gcc/common/config/riscv/riscv-common.cc |  2 ++
 gcc/config/riscv/riscv-builtins.cc  |  6 --
 gcc/config/riscv/riscv-opts.h   |  2 ++
 gcc/config/riscv/riscv.md   |  7 ++-
 gcc/testsuite/gcc.target/riscv/builtin_pause.c  | 10 --
 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause.c| 11 +++
 7 files changed, 36 insertions(+), 13 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 2eb8c7cadff0..02502ba07e82 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -209,6 +209,7 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
   {"zkt",   ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"zihintntl", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zihintpause", ISA_SPEC_CLASS_NONE, 2, 0},
 
   {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0},
   {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1344,6 +1345,7 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
   {"zkt",_options::x_riscv_zk_subext, MASK_ZKT},
 
   {"zihintntl", _options::x_riscv_zi_subext, MASK_ZIHINTNTL},
+  {"zihintpause", _options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
 
   {"zicboz", _options::x_riscv_zicmo_subext, MASK_ZICBOZ},
   {"zicbom", _options::x_riscv_zicmo_subext, MASK_ZICBOM},
diff --git a/gcc/config/riscv/riscv-builtins.cc 
b/gcc/config/riscv/riscv-builtins.cc
index 79681d759628..554fb7f69bb0 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -122,7 +122,8 @@ AVAIL (clmul_zbkc32_or_zbc32, (TARGET_ZBKC || TARGET_ZBC) 
&& !TARGET_64BIT)
 AVAIL (clmul_zbkc64_or_zbc64, (TARGET_ZBKC || TARGET_ZBC) && TARGET_64BIT)
 AVAIL (clmulr_zbc32, TARGET_ZBC && !TARGET_64BIT)
 AVAIL (clmulr_zbc64, TARGET_ZBC && TARGET_64BIT)
-AVAIL (always, (!0))
+AVAIL (hint_pause, TARGET_ZIHINTPAUSE)
+AVAIL (hint_pause_pseudo, !TARGET_ZIHINTPAUSE)
 
 /* Construct a riscv_builtin_description from the given arguments.
 
@@ -179,7 +180,8 @@ static const struct riscv_builtin_description 
riscv_builtins[] = {
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
-  DIRECT_NO_TARGET_BUILTIN (pause, RISCV_VOID_FTYPE, always),
+  RISCV_BUILTIN (pause, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE, hint_pause),
+  RISCV_BUILTIN (pause_insn, "pause", RISCV_BUILTIN_DIRECT_NO_TARGET, 
RISCV_VOID_FTYPE, hint_pause_pseudo),
 };
 
 /* Index I is the function declaration for riscv_builtins[I], or null if the
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 28d9b81bd800..a6c3e0c9098f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -102,10 +102,12 @@ enum riscv_entity
 #define MASK_ZICSR(1 << 0)
 #define MASK_ZIFENCEI (1 << 1)
 #define MASK_ZIHINTNTL (1 << 2)
+#define MASK_ZIHINTPAUSE (1 << 3)
 
 #define TARGET_ZICSR  

[RFC PATCH 0/2] RISC-V: __builtin_riscv_pause for all environment

[Tsukasa OI via Gcc-patches]

Hello,

I found that a built-in function "__builtin_riscv_pause" is not usable
unless we enable the 'Zihintpause' extension explicitly (still, this
built-in exists EVEN IF the 'Zihintpause' extension is disabled).

Contents of a.c:

> void sample(void)
> {
> __builtin_riscv_pause();
> }


Compiling with the 'Zihintpause' extension is fine.

> $ riscv64-unknown-elf-gcc -O2 -march=rv64i_zihintpause -mabi=lp64 -c a.c


However, compiling without the 'Zihintpause' causes an assembler error
(tested with GNU Binutils 2.41):

> $ riscv64-unknown-elf-gcc -O2 -march=rv64i -mabi=lp64 -c a.c
> /tmp/ccFjacAz.s: Assembler messages:
> /tmp/ccFjacAz.s:11: Error: unrecognized opcode `pause', extension 
> `zihintpause' required


This is because:

1.  GCC does not handle the 'Zihintpause' extension and
2.  "riscv_pause" (insn) unconditionally emits "pause" even if the
assembler does not accept it (when the extension is disabled).


This patch set (PATCH 1/2) resolves this issue by:

1.  Handling the 'Zihintpause' extension and
2.  Splitting the "__builtin_riscv_pause" implementation
depending on the existence of the 'Zihintpause' extension.

Because a released version of GCC defines "__builtin_riscv_pause"
unconditionally, I chose to define no-'Zihintpause' version.

There is another option to unconditionally emit ".insn 0x010f"
(the machine code of "pause") but I didn't because I wanted to improve the
diagnostics (e.g. *.s output).

I also fixed the description of this built-in function (in PATCH 2/2).


I'm not sure whether this is a good method to split the implementation
depending on the 'Zihintpause' extension.  Other than that, I believe that
this is okay and approval is appreciated.

Note that because I assigned copyright of GCC contribution to FSF, I didn't
attach "Signed-off-by" tag.  Tell me if I need it.

Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: __builtin_riscv_pause for all environment
  RISC-V: Fix documentation of __builtin_riscv_pause

 gcc/common/config/riscv/riscv-common.cc |  2 ++
 gcc/config/riscv/riscv-builtins.cc  |  6 --
 gcc/config/riscv/riscv-opts.h   |  2 ++
 gcc/config/riscv/riscv.md   |  7 ++-
 gcc/doc/extend.texi |  6 +++---
 gcc/testsuite/gcc.target/riscv/builtin_pause.c  | 10 --
 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c | 11 +++
 gcc/testsuite/gcc.target/riscv/zihintpause.c| 11 +++
 8 files changed, 39 insertions(+), 16 deletions(-)
 delete mode 100644 gcc/testsuite/gcc.target/riscv/builtin_pause.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause-noarch.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zihintpause.c


base-commit: c8b396243ec5bfa9b541555131df597ebc84b9d0
-- 
2.41.0

[PATCH] RISC-V: Remove non-existing 'Zve32d' extension

[Tsukasa OI via Gcc-patches]

From: Tsukasa OI 

Since this extension does not exist, this commit prunes this from
the defined extension version table.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc(riscv_ext_version_table):
Remove 'Zve32d' from the version list.
---
 gcc/common/config/riscv/riscv-common.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 2eb8c7cadff0..f25131eab28b 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -220,7 +220,6 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0},
-  {"zve32d", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zve64x", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zve64f", ISA_SPEC_CLASS_NONE, 1, 0},
   {"zve64d", ISA_SPEC_CLASS_NONE, 1, 0},

base-commit: c8b396243ec5bfa9b541555131df597ebc84b9d0
-- 
2.41.0

Re: [PATCH 1/1] RISC-V: Fix canonical extension order (K and J)

[Tsukasa OI via Gcc-patches]

On 2022/05/19 12:40, Nelson Chu wrote:
> Seems like gcc and llvm have already committed this patch, so LGTM, committed.

Sorry, the same change is applied to LLVM but not yet on GCC (because I
forgot to add "Signed-off-by" line).  I sent PATCH v2 to gcc-patches
today so that would be okay.  On PATCH v2, I made the same change to
gcc/config/riscv/arch-canonicalize script (not just
gcc/common/config/riscv/riscv-common.cc).



Thanks,
Tsukasa

> 
> Thanks
> Nelson
> 
> On Mon, Apr 25, 2022 at 11:53 AM Palmer Dabbelt  wrote:
>>
>> On Mon, 28 Mar 2022 17:12:55 PDT (-0700), Palmer Dabbelt wrote:
>>> On Mon, 28 Mar 2022 06:12:01 PDT (-0700), binut...@sourceware.org wrote:
 This commit fixes canonical extension order to follow the RISC-V ISA
 Manual draft-20210402-1271737 or later.

 bfd/ChangeLog:

  * elfxx-riscv.c (riscv_recognized_prefixed_ext): Fix "K" extension
  prefix to be placed before "J".
 ---
  bfd/elfxx-riscv.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
 index cb2cc146c04..1219a7b44d4 100644
 --- a/bfd/elfxx-riscv.c
 +++ b/bfd/elfxx-riscv.c
 @@ -1338,7 +1338,7 @@ riscv_recognized_prefixed_ext (const char *ext)
  }

  /* Canonical order for single letter extensions.  */
 -static const char riscv_ext_canonical_order[] = "eigmafdqlcbjktpvn";
 +static const char riscv_ext_canonical_order[] = "eigmafdqlcbkjtpvn";

  /* Array is used to compare the orders of standard extensions quickly.  */
  static int riscv_ext_order[26] = {0};
>>>
>>> Looks like this was just a bug in binutils: K went from being
>>> unspecified to specified in 271737 ("Define canonical location of K
>>> extension in ISA string"), thus it was never allowed at that other bit
>>> position.
>>>
>>> It looks like GCC also has this wrong, which sort of doubles the
>>> headache: now we've got this odd coupling between the GCC version and
>>> binutils version.  I'm not sure what the right thing is to do here:
>>> certainly rejecting the valid ISA string should be fixed, but I think we
>>> might need to accept the invalid one for compatibility reasons.  That'll
>>> be a headache to implement, though, so I'm not sure it's worth it.
>>>
>>> Maybe someone has a clever solution to this one?
>>
>> After seeing the GCC patch go by, I think the clever solution here is to
>> just say that we never accepted any J stuff in the first place so it's
>> not a compatibility break.
> 

[PATCH v2 1/1] RISC-V: Fix canonical extension order (K and J)

[Tsukasa OI via Gcc-patches]

This commit fixes canonical extension order to follow the RISC-V ISA
Manual draft-20210402-1271737 or later.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_supported_std_ext):
Fix "K" extension prefix to be placed before "J".
* config/riscv/arch-canonicalize: Likewise.

Signed-off-by: Tsukasa OI 
---
 gcc/common/config/riscv/riscv-common.cc | 2 +-
 gcc/config/riscv/arch-canonicalize  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..0b0ec2c4ec5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -594,7 +594,7 @@ riscv_subset_list::lookup (const char *subset, int 
major_version,
 static const char *
 riscv_supported_std_ext (void)
 {
-  return "mafdqlcbjktpvn";
+  return "mafdqlcbkjtpvn";
 }
 
 /* Parsing subset version.
diff --git a/gcc/config/riscv/arch-canonicalize 
b/gcc/config/riscv/arch-canonicalize
index 41bab69193c..71b2232b29e 100755
--- a/gcc/config/riscv/arch-canonicalize
+++ b/gcc/config/riscv/arch-canonicalize
@@ -32,7 +32,7 @@ import itertools
 from functools import reduce
 
 SUPPORTED_ISA_SPEC = ["2.2", "20190608", "20191213"]
-CANONICAL_ORDER = "imafdgqlcbjktpvn"
+CANONICAL_ORDER = "imafdgqlcbkjtpvn"
 LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
 
 #
-- 
2.34.1

[PATCH v2 0/1] RISC-V: Fix canonical extension order (K and J)

[Tsukasa OI via Gcc-patches]

PATCH v1:


Changes between v1 and v2:
-   Added Signed-off-by line (I didn't notice that this is required)
-   Applied the same change to Python script:
gcc/config/riscv/arch-canonicalize

Note that this kind of change is already made in GNU Binutils and LLVM.
GNU Binutils: commit c4dd8eb523fae5c9d312f4b7b21377eec66e70c3
LLVM: commit 7fe0630fcb6d52cb63463669c47f4846f7d9ccbf




Tsukasa OI (1):
  RISC-V: Fix canonical extension order (K and J)

 gcc/common/config/riscv/riscv-common.cc | 2 +-
 gcc/config/riscv/arch-canonicalize  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)


base-commit: a60228404f2ac11b5eb66270037ff3fa6bf948e5
-- 
2.34.1

Re: [PATCH 1/1] RISC-V: Fix canonical extension order (K and J)

[Tsukasa OI via Gcc-patches]

Hello,

> Neither K nor J is an extension that exists,

That is correct.

> and so it doesn't make
> sense to mandate any particular ordering.

No. It affects Z* extension ordering...


On 2022/04/24 14:36, Andrew Waterman wrote:
> Neither K nor J is an extension that exists, and so it doesn't make
> sense to mandate any particular ordering.  The better change would be
> to delete the letters `k' and `j' from that string, so that we aren't
> enforcing constraints that don't serve a useful purpose.
> 
> cf. 
> https://github.com/riscv/riscv-isa-manual/commit/f5f9c27010b69a015958ffebe1ac5a34f8776dff

Wait... so, you make constraints for existing single-letters (Zi -> Zv)
but not for non-existing single-letters? (Zk -> Zj, Zj -> Zk) anymore?

That's completely unexpected move but also makes sense.

Let me check your intentions and details: do we need to place Z[CH]*
extensions without single-letter extension [CH] after all existing ones
(like Zv*)? Or, Z[CH]* extensions without single-letter extension [CH]
have no constraints as long as all Z* extensions are grouped together?

> 
> On Sat, Apr 23, 2022 at 10:26 PM Tsukasa OI via Gcc-patches
>  wrote:
>>
>> This commit fixes canonical extension order to follow the RISC-V ISA
>> Manual draft-20210402-1271737 or later.
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc (riscv_supported_std_ext):
>> Fix "K" extension prefix to be placed before "J".
>> ---
>>  gcc/common/config/riscv/riscv-common.cc | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gcc/common/config/riscv/riscv-common.cc 
>> b/gcc/common/config/riscv/riscv-common.cc
>> index 1501242e296..0b0ec2c4ec5 100644
>> --- a/gcc/common/config/riscv/riscv-common.cc
>> +++ b/gcc/common/config/riscv/riscv-common.cc
>> @@ -594,7 +594,7 @@ riscv_subset_list::lookup (const char *subset, int 
>> major_version,
>>  static const char *
>>  riscv_supported_std_ext (void)
>>  {
>> -  return "mafdqlcbjktpvn";
>> +  return "mafdqlcbkjtpvn";
>>  }
>>
>>  /* Parsing subset version.
>> --
>> 2.32.0
>>
> 

[PATCH 1/1] RISC-V: Fix canonical extension order (K and J)

[Tsukasa OI via Gcc-patches]

This commit fixes canonical extension order to follow the RISC-V ISA
Manual draft-20210402-1271737 or later.

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_supported_std_ext):
Fix "K" extension prefix to be placed before "J".
---
 gcc/common/config/riscv/riscv-common.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 1501242e296..0b0ec2c4ec5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -594,7 +594,7 @@ riscv_subset_list::lookup (const char *subset, int 
major_version,
 static const char *
 riscv_supported_std_ext (void)
 {
-  return "mafdqlcbjktpvn";
+  return "mafdqlcbkjtpvn";
 }
 
 /* Parsing subset version.
-- 
2.32.0

[PATCH 0/1] RISC-V: Fix canonical extension order (K and J)

[Tsukasa OI via Gcc-patches]

**note**

My copyright assignment to FSF is not yet started (will start just after
sending this patch).  Please take care of the assignment status.



This patch fixes RISC-V's canonical extension order...
from: "J" -> "K"
to  : "K" -> "J"
as per the RISC-V ISA Manual draft-20210402-1271737 or later.

This bug in the GCC is currently harmless because neither J nor
Zj* extensions are implemented.  Intention of this commit is for future-
proofness.

This patch corresponds following patch for GNU Binutils:

[My copyright assignment is done on GNU Binutils]

References:






Tsukasa OI (1):
  RISC-V: Fix canonical extension order (K and J)

 gcc/common/config/riscv/riscv-common.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


base-commit: ab54f6007c79711fc2192098d4ccc3c24e95f3e6
-- 
2.32.0