Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Umesh Kalappa]

Ok, thanks for the clarification jakub.

Umesg

On Mon, May 7, 2018, 2:08 PM Jakub Jelinek  wrote:

> On Mon, May 07, 2018 at 01:58:48PM +0530, Umesh Kalappa wrote:
> > CCed Jakub,
>
> > > Agree that float division don't touch memory ,but fdiv  result (stack
> > > register ) is stored  back to a memory i.e fResult .
>
> That doesn't really matter.  It is stored to a stack spill slot, something
> that doesn't have address taken and other code (e.g. in other threads)
> can't
> in a valid program access it.  That is not considered memory for the
> inline-asm, only objects that must live in memory count.
>
> Jakub
>

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Jakub Jelinek]

On Mon, May 07, 2018 at 01:58:48PM +0530, Umesh Kalappa wrote:
> CCed Jakub,

> > Agree that float division don't touch memory ,but fdiv  result (stack
> > register ) is stored  back to a memory i.e fResult .

That doesn't really matter.  It is stored to a stack spill slot, something
that doesn't have address taken and other code (e.g. in other threads) can't
in a valid program access it.  That is not considered memory for the
inline-asm, only objects that must live in memory count.

Jakub

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Umesh Kalappa]

CCed Jakub,


> Hi Alex,
> Agree that float division don't touch memory ,but fdiv  result (stack
> register ) is stored  back to a memory i.e fResult .
>
> So compiler barrier in the inline asm i.e ::memory should prevent the
> shrinkage of  instructions like  "fstps   fResult(%rip)"behind the
> fence ?
>
> BTW ,if we make fDivident  and  fResult = 0.0f  gloabls,the code
> emitted looks ok  i.e
> #gcc -S test.c -O3  -mmmx -mno-sse
>
>flds.LC0(%rip)
> fstsfDivident(%rip)
> fdivs   .LC1(%rip)
> fstps   fResult(%rip)
> #APP
> # 10 "test.c" 1
> mfence
> # 0 "" 2
> #NO_APP
> fldsfResult(%rip)
> movl$.LC2, %edi
> xorl%eax, %eax
> fstpl   (%rsp)
> callprintf
>
> So i strongly believe that ,its compiler issue and please feel free
> correct me in any case.
>
> Thank you and waiting for your reply.
>
> ~Umesh
>
>
>
>
> On Fri, Apr 13, 2018 at 5:58 PM, Alexander Monakov  wrote:
>> On Fri, 13 Apr 2018, Vivek Kinhekar wrote:
>>> The mfence instruction with memory clobber asm instruction should create a
>>> barrier between division and printf instructions.
>>
>> No, floating-point division does not touch memory, so the asm does not (and
>> need not) restrict its motion.
>>
>> Alexander

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Umesh Kalappa]

Hi Alex ,

Agree that float division don't touch memory ,but fdiv  result (stack
register ) is stored  back to a memory i.e fResult .

So compiler barrier in the inline asm i.e ::memory should prevent the
shrinkage of  instructions like  "fstps   fResult(%rip)"behind the
fence ?

BTW ,if we make fDivident  and  fResult = 0.0f  gloabls,the code
emitted looks ok  i.e
#gcc -S test.c -O3  -mmmx -mno-sse

   flds.LC0(%rip)
fstsfDivident(%rip)
fdivs   .LC1(%rip)
fstps   fResult(%rip)
#APP
# 10 "test.c" 1
mfence
# 0 "" 2
#NO_APP
fldsfResult(%rip)
movl$.LC2, %edi
xorl%eax, %eax
fstpl   (%rsp)
callprintf

So i strongly believe that ,its compiler issue and please feel free
correct me in any case.

Thank you and waiting for your reply.

~Umesh




On Fri, Apr 13, 2018 at 5:58 PM, Alexander Monakov  wrote:
> On Fri, 13 Apr 2018, Vivek Kinhekar wrote:
>> The mfence instruction with memory clobber asm instruction should create a
>> barrier between division and printf instructions.
>
> No, floating-point division does not touch memory, so the asm does not (and
> need not) restrict its motion.
>
> Alexander

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Jakub Jelinek]

On Fri, Apr 13, 2018 at 01:34:21PM +, Vivek Kinhekar wrote:
> Hello Alexander,
> 
> In the given testcase, the generated fdivrs instruction performs the
> division of a symbol ref (memory value) by FPU Stack Register and stores
> the value in FPU Stack Register.

The stack registers are not memory.

> Please find the following RTL Dump of the fdivrs instruction generated. 
> It clearly access the memory for read access! 

That is a constant read, that doesn't count either.  It is in memory only
because the instruction doesn't support constant immediates, the memory is
read-only.

Jakub

RE: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Vivek Kinhekar]

Oh! Thanks for the quick response, Jakub.

Regards,
Vivek Kinhekar

-Original Message-
From: Jakub Jelinek <ja...@redhat.com> 
Sent: Friday, April 13, 2018 7:08 PM
To: Vivek Kinhekar <vivek.kinhe...@blackfigtech.com>
Cc: Alexander Monakov <amona...@ispras.ru>; gcc@gcc.gnu.org
Subject: Re: GCC Compiler Optimization ignores or mistreats MFENCE memory 
barrier related instruction

On Fri, Apr 13, 2018 at 01:34:21PM +, Vivek Kinhekar wrote:
> Hello Alexander,
> 
> In the given testcase, the generated fdivrs instruction performs the 
> division of a symbol ref (memory value) by FPU Stack Register and 
> stores the value in FPU Stack Register.

The stack registers are not memory.

> Please find the following RTL Dump of the fdivrs instruction generated. 
> It clearly access the memory for read access! 

That is a constant read, that doesn't count either.  It is in memory only 
because the instruction doesn't support constant immediates, the memory is 
read-only.

Jakub

RE: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Vivek Kinhekar]

Hello Alexander,

In the given testcase, the generated fdivrs instruction performs the division 
of a symbol ref (memory value) by FPU Stack Register and stores the value in 
FPU Stack Register. 

Please find the following RTL Dump of the fdivrs instruction generated. It 
clearly access the memory for read access!
===
#(insn:TI 13 20 16 2 (set (reg:XF 8 st)
#(div:XF (float_extend:XF (mem/u/c:SF (symbol_ref/u:SI ("*.LC0") [flags 
0x2]) [4 S4 A32]))
#(reg:XF 8 st)))  {*fop_xf_4_i387}
# (nil))
fdivrs  .LC0# 13*fop_xf_4_i387/1[length = 6]
===

Are we missing anything subtle here?

Regards,
Vivek Kinhekar

-Original Message-
From: Alexander Monakov <amona...@ispras.ru> 
Sent: Friday, April 13, 2018 5:58 PM
To: Vivek Kinhekar <vivek.kinhe...@blackfigtech.com>
Cc: gcc@gcc.gnu.org
Subject: Re: GCC Compiler Optimization ignores or mistreats MFENCE memory 
barrier related instruction

On Fri, 13 Apr 2018, Vivek Kinhekar wrote:
> The mfence instruction with memory clobber asm instruction should 
> create a barrier between division and printf instructions.

No, floating-point division does not touch memory, so the asm does not (and 
need not) restrict its motion.

Alexander

RE: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Vivek Kinhekar]

Thanks for the quick response, Alexander!

Regards,
Vivek Kinhekar
+91-7709046470

-Original Message-
From: Alexander Monakov <amona...@ispras.ru> 
Sent: Friday, April 13, 2018 5:58 PM
To: Vivek Kinhekar <vivek.kinhe...@blackfigtech.com>
Cc: gcc@gcc.gnu.org
Subject: Re: GCC Compiler Optimization ignores or mistreats MFENCE memory 
barrier related instruction

On Fri, 13 Apr 2018, Vivek Kinhekar wrote:
> The mfence instruction with memory clobber asm instruction should 
> create a barrier between division and printf instructions.

No, floating-point division does not touch memory, so the asm does not (and 
need not) restrict its motion.

Alexander

Re: GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Alexander Monakov]

On Fri, 13 Apr 2018, Vivek Kinhekar wrote:
> The mfence instruction with memory clobber asm instruction should create a
> barrier between division and printf instructions.

No, floating-point division does not touch memory, so the asm does not (and
need not) restrict its motion.

Alexander

GCC Compiler Optimization ignores or mistreats MFENCE memory barrier related instruction

[Vivek Kinhekar]

Hi,


We are trying to create a memory barrier with following testcase.

=
#include 

void Test()
{
float fDivident = 0.1f;
float fResult = 0.0f;

fResult = ( fDivident / fResult );

__asm volatile ("mfence" ::: "memory");

printf("\nResult: %f\n", fResult);
}
==



'mfence' performs a serializing operation on all load-from-memory and 
store-to-memory instructions that were issued prior the MFENCE instruction. 
This serializing operation guarantees that every load and store instruction 
that precedes the MFENCE instruction in program order becomes globally visible 
before any load or store instruction that follows the MFENCE instruction.

The mfence instruction with memory clobber asm instruction should create a 
barrier between division and printf instructions.



When the testcase is compiled with optimization options O1 and above it can be 
observed that the mfence instruction is reordered and precedes division 
instruction.

We expected that the two sets of assembly instructions, one pertaining to 
division operation and another pertaining to the printf operation, would not 
get mixed up on reordering by the GCC compiler optimizer because of the 
presence of the __asm volatile ("mfence" ::: "memory"); line between them.



But, the generated assembly, which is inlined below for reference, isn't quite 
right as per our expectation.



pushl   %ebp# 23*pushsi2[length = 1]
movl%esp, %ebp  # 24*movsi_internal/1   [length = 2]
subl$24, %esp   # 25pro_epilogue_adjust_stack_si_add/1  
[length = 3]
mfence
fldz# 20*movxf_internal/3   [length = 2]
fdivrs  .LC0# 13*fop_xf_4_i387/1[length = 6]

You may note that the mfence instruction is generated before the fdivrs 
instruction.

Can you please let us know if the usage of the "asm (mfence)" instruction as 
given in the above testcase is the right way of creating the expected memory 
barrier between the two sets of instructions pertaining to the division and 
printf operations, respectively or not?

If yes, then we think, it's a bug in Compiler. Could you please confirm?

If no, then what is the correct usage of "asm (mfence)" so as to get/ achieve 
the memory barrier functionality as expected in the above testcase?

Thanks,
Vivek Kinhekar