[Bug target/70119] AArch64 should take advantage of implicit truncation of variable shift amount without defining SHIFT_COUNT_TRUNCATED
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70119 --- Comment #6 from collison at gcc dot gnu.org --- Author: collison Date: Thu Jun 29 09:21:57 2017 New Revision: 249774 URL: https://gcc.gnu.org/viewcvs?rev=249774=gcc=rev Log: 2017-06-29 Kyrylo Tkachov <kyrylo.tkac...@arm.com> Michael Collison <michael.colli...@arm.com> PR target/70119 * config/aarch64/aarch64.md (*aarch64__reg_3_mask1): New pattern. (*aarch64_reg_3_neg_mask2): New pattern. (*aarch64_reg_3_minus_mask): New pattern. (*aarch64__reg_di3_mask2): New pattern. * config/aarch64/aarch64.c (aarch64_rtx_costs): Account for cost of shift when the shift amount is masked with constant equal to the size of the mode. * config/aarch64/predicates.md (subreg_lowpart_operator): New predicate. 2017-06-29 Kyrylo Tkachov <kyrylo.tkac...@arm.com> Michael Collison <michael.colli...@arm.com> PR target/70119 * gcc.target/aarch64/var_shift_mask_1.c: New test. Added: trunk/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/aarch64/aarch64.c trunk/gcc/config/aarch64/aarch64.md trunk/gcc/config/aarch64/predicates.md trunk/gcc/testsuite/ChangeLog
[Bug target/68535] arm.c: 5 * set but not used
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68535 --- Comment #3 from collison at gcc dot gnu.org --- Author: collison Date: Wed Jun 28 07:07:49 2017 New Revision: 249721 URL: https://gcc.gnu.org/viewcvs?rev=249721=gcc=rev Log: 2017-06-28 Michael Collison <michael.colli...@arm.com> PR target/68535 * config/arm/arm.c (gen_ldm_seq): Remove last unnecessary set of base_reg (arm_gen_movmemqi): Removed unused variable 'i'. Convert 'for' loop into 'while' loop. (arm_expand_prologue): Remove last unnecessary set of insn. (thumb_pop): Remove unused variable 'pushed_words'. (thumb_exit): Remove last unnecessary set of regs_to_pop. Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm.c
[Bug target/70014] [ARM] Predicate does not match constraint (*subsi3_carryin_const)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=70014 --- Comment #2 from collison at gcc dot gnu.org --- Author: collison Date: Thu Mar 3 07:42:02 2016 New Revision: 233927 URL: https://gcc.gnu.org/viewcvs?rev=233927=gcc=rev Log: 2016-03-03 Michael Collison <michael.colli...@linaro.org> PR target/70014 * config/arm/arm.md (*subsi3_carryin_const): Change predicate for operand 1 to s_register_operand. Change predicate for operand 2 to arm_not_immediate_operand. Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm.md
[Bug other/57195] Mode attributes with specific mode iterator can not be used as mode iterators in *.md files
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57195 --- Comment #7 from collison at gcc dot gnu.org --- Author: collison Date: Thu Sep 24 23:26:50 2015 New Revision: 228102 URL: https://gcc.gnu.org/viewcvs?rev=228102=gcc=rev Log: 2015-09-24 Michael Collison <michael.colli...@linaro.org> PR other/57195 * read-md.c (read_name): Allow mode iterators inside angle brackets in rtl expressions. Modified: trunk/gcc/ChangeLog trunk/gcc/read-md.c
[Bug target/61915] [AArch64] High amounts of GP to FP register moves using LRA on AArch64 - Improve Generic register_move_cost and memory_move_cost
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61915 --- Comment #23 from collison at gcc dot gnu.org --- Author: collison Date: Tue Mar 10 07:34:20 2015 New Revision: 221302 URL: https://gcc.gnu.org/viewcvs?rev=221302root=gccview=rev Log: 2015-03-10 Michael Collison michael.colli...@linaro.org Backport from trunk r217780. 2014-11-19 Wilco Dijkstra wdijk...@arm.com PR target/61915 * config/aarch64/aarch64.c (generic_regmove_cost): Increase FP move cost. Modified: branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro branches/linaro/gcc-4_9-branch/gcc/config/aarch64/aarch64.c
[Bug target/63293] [AArch64] can read from deallocated stack
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63293 --- Comment #6 from collison at gcc dot gnu.org --- Author: collison Date: Tue Feb 10 08:17:09 2015 New Revision: 220574 URL: https://gcc.gnu.org/viewcvs?rev=220574root=gccview=rev Log: 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r217091. 2014-11-04 Jiong Wang jiong.w...@arm.com 2014-11-04 Wilco Dijkstra wilco.dijks...@arm.com PR target/63293 * config/aarch64/aarch64.c (aarch64_expand_epiloue): Add barriers before stack adjustment. Modified: branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro branches/linaro/gcc-4_9-branch/gcc/config/aarch64/aarch64.c
[Bug rtl-optimization/63676] [5.0 regression] vshuf-v16hi.c ICE on arm-none-eabi
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63676 --- Comment #3 from collison at gcc dot gnu.org --- Author: collison Date: Tue Feb 10 08:05:35 2015 New Revision: 220572 URL: https://gcc.gnu.org/viewcvs?rev=220572root=gccview=rev Log: 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r217215. 2014-11-07 Jiong Wang jiong.w...@arm.com 2014-11-07 Richard Biener rguent...@suse.de PR tree-optimization/63676 * gimple-fold.c (fold_gimple_assign): Do not fold node when TREE_CLOBBER_P be true. Modified: branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro branches/linaro/gcc-4_9-branch/gcc/gimple-fold.c
[Bug tree-optimization/61114] Scalar evolution hides a big-endian const-folding bug.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61114 --- Comment #12 from collison at gcc dot gnu.org --- Author: collison Date: Tue Feb 10 02:23:40 2015 New Revision: 220562 URL: https://gcc.gnu.org/viewcvs?rev=220562root=gccview=rev Log: 2015-02-09 Michael Collison michael.colli...@linaro.org Backport from trunk r216779. 2014-10-28 Alan Lawrence alan.lawre...@arm.com * expr.c (expand_expr_real_2): Remove code handling VEC_LSHIFT_EXPR. * fold-const.c (const_binop): Likewise. * cfgexpand.c (expand_debug_expr): Likewise. * tree-inline.c (estimate_operator_cost): Likewise. * tree-vect-generic.c (expand_vector_operations_1): Likewise. * optabs.c (optab_for_tree_code): Likewise. (expand_vec_shift_expr): Likewise, update comment. * tree.def: Delete VEC_LSHIFT_EXPR, remove comment. * optabs.h (expand_vec_shift_expr): Remove comment re. VEC_LSHIFT_EXPR. * optabs.def: Remove vec_shl_optab. * doc/md.texi: Remove references to vec_shr_m. 2015-02-09 Michael Collison michael.colli...@linaro.org Backport from trunk r216742. 2014-10-27 Alan Lawrence alan.lawre...@arm.com * config/aarch64/aarch64.c (TARGET_GIMPLE_FOLD_BUILTIN): Define again. * config/aarch64/aarch64-builtins.c (aarch64_gimple_fold_builtin): Restore, enable for bigendian, update to use __builtin..._scal... 2015-02-09 Michael Collison michael.colli...@linaro.org Backport from trunk r216741. 2014-10-27 Alan Lawrence alan.lawre...@arm.com * config/aarch64/aarch64-simd-builtins.def (reduc_smax_, reduc_smin_, reduc_umax_, reduc_umin_, reduc_smax_nan_, reduc_smin_nan_): Remove. (reduc_smax_scal_, reduc_smin_scal_, reduc_umax_scal_, reduc_umin_scal_, reduc_smax_nan_scal_, reduc_smin_nan_scal_): New. * config/aarch64/aarch64-simd.md (reduc_maxmin_uns_mode): Rename VDQV_S variant to... (reduc_maxmin_uns_internalmode): ...this. (reduc_maxmin_uns_mode): New (VDQ_BHSI). (reduc_maxmin_uns_scal_mode): New (*2). (reduc_maxmin_uns_v2si): Combine with below, renaming... (reduc_maxmin_uns_mode): Combine V2F with above, renaming... (reduc_maxmin_uns_internal_mode): ...to this (VDQF). * config/aarch64/arm_neon.h (vmaxv_f32, vmaxv_s8, vmaxv_s16, vmaxv_s32, vmaxv_u8, vmaxv_u16, vmaxv_u32, vmaxvq_f32, vmaxvq_f64, vmaxvq_s8, vmaxvq_s16, vmaxvq_s32, vmaxvq_u8, vmaxvq_u16, vmaxvq_u32, vmaxnmv_f32, vmaxnmvq_f32, vmaxnmvq_f64, vminv_f32, vminv_s8, vminv_s16, vminv_s32, vminv_u8, vminv_u16, vminv_u32, vminvq_f32, vminvq_f64, vminvq_s8, vminvq_s16, vminvq_s32, vminvq_u8, vminvq_u16, vminvq_u32, vminnmv_f32, vminnmvq_f32, vminnmvq_f64): Update to use __builtin_aarch64_reduc_..._scal; remove vget_lane wrapper. 2015-02-09 Michael Collison michael.colli...@linaro.org Backport from trunk r216738. 2014-10-27 Alan Lawrence alan.lawre...@arm.com * config/aarch64/aarch64-simd-builtins.def (reduc_splus_mode/VDQF, reduc_uplus_mode/VDQF, reduc_splus_v4sf): Remove. (reduc_plus_scal_mode, reduc_plus_scal_v4sf): New. * config/aarch64/aarch64-simd.md (reduc_surplus_mode): Remove. (reduc_splus_mode, reduc_uplus_mode, reduc_plus_scal_mode): New. (reduc_surplus_mode): Change SUADDV - UNSPEC_ADDV, rename to... (aarch64_reduc_plus_internalmode): ...this. (reduc_surplus_v2si): Change SUADDV - UNSPEC_ADDV, rename to... (aarch64_reduc_plus_internalv2si): ...this. (reduc_splus_mode/V2F): Rename to... (aarch64_reduc_plus_internalmode): ...this. * config/aarch64/iterators.md (UNSPEC_SADDV, UNSPEC_UADDV, SUADDV): Remove. (UNSPEC_ADDV): New. (sur): Remove elements for UNSPEC_SADDV and UNSPEC_UADDV. * config/aarch64/arm_neon.h (vaddv_s8, vaddv_s16, vaddv_s32, vaddv_u8, vaddv_u16, vaddv_u32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vaddvq_s64, vaddvq_u8, vaddvq_u16, vaddvq_u32, vaddvq_u64, vaddv_f32, vaddvq_f32, vaddvq_f64): Change __builtin_aarch64_reduc_[us]plus_... to __builtin_aarch64_reduc_plus_scal, remove vget_lane wrapper. 2015-02-09 Michael Collison michael.colli...@linaro.org Backport from trunk r216737. 2014-10-27 Alan Lawrence alan.lawre...@arm.com PR tree-optimization/61114 * doc/md.texi (Standard Names): Add reduc_(plus,[us](min|max))|scal optabs, and note in reduc_[us](plus|min|max) to prefer the former. * expr.c (expand_expr_real_2): Use reduc_..._scal if available, fall back to old reduc_... BIT_FIELD_REF only if not. * optabs.c (optab_for_tree_code): for REDUC_(MAX,MIN,PLUS)_EXPR, return the reduce-to-scalar (reduc_..._scal) optab. (scalar_reduc_to_vector): New. * optabs.def (reduc_smax_scal_optab, reduc_smin_scal_optab, reduc_plus_scal_optab, reduc_umax_scal_optab, reduc_umin_scal_optab): New. * optabs.h (scalar_reduc_to_vector): Declare. * tree-vect-loop.c (vectorizable_reduction): Look for optabs reducing to either scalar or vector. 2015-02
[Bug target/64460] ARM ICE on valid code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64460 --- Comment #13 from collison at gcc dot gnu.org --- Author: collison Date: Tue Feb 10 07:53:23 2015 New Revision: 220570 URL: https://gcc.gnu.org/viewcvs?rev=220570root=gccview=rev Log: 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r219583. 2015-01-14 Kyrylo Tkachov kyrylo.tkac...@arm.com PR target/64460 * config/arm/arm.md (*arith_shift_insn_multsi): Set 'shift' to 2. (*arith_shift_insn_shiftsi): Set 'shift' attr to 3. 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r217430. 2014-11-12 Ramana Radhakrishnan ramana.radhakrish...@arm.com * config/arm/arm.c (*arith_shift_insn_shiftsi): Fix typo. 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r219583. 2015-01-14 Kyrylo Tkachov kyrylo.tkac...@arm.com PR target/64460 * gcc.target/arm/pr64460_1.c: New test. Added: branches/linaro/gcc-4_9-branch/gcc/testsuite/gcc.target/arm/pr64460_1.c Modified: branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro branches/linaro/gcc-4_9-branch/gcc/config/arm/arm.md branches/linaro/gcc-4_9-branch/gcc/testsuite/ChangeLog.linaro
[Bug target/64011] Fail to compile pr48335-2.c on big-endian where bit insert instruction supported
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64011 --- Comment #5 from collison at gcc dot gnu.org --- Author: collison Date: Tue Feb 10 07:31:25 2015 New Revision: 220568 URL: https://gcc.gnu.org/viewcvs?rev=220568root=gccview=rev Log: 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r219718. * expmed.c (store_bit_field_using_insv): Improve warning message. Use %wu instead of HOST_WIDE_INT_PRINT_UNSIGNED. 2015-01-15 Jiong Wang jiong.w...@arm.com 2015-02-10 Michael Collison michael.colli...@linaro.org Backport from trunk r219717. 2015-01-15 Jiong Wang jiong.w...@arm.com PR rtl-optimization/64011 * expmed.c (store_bit_field_using_insv): Warn and truncate bitsize when there is partial overflow. Modified: branches/linaro/gcc-4_9-branch/gcc/ChangeLog.linaro branches/linaro/gcc-4_9-branch/gcc/expmed.c
