from:"jeremy.bennett at embecosm dot com via Gcc\-bugs"

[Bug target/115093] New: RISC-V Vector ICE in extract_insn: unrecognizable insn

2024-05-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115093

Bug ID: 115093
   Summary: RISC-V Vector ICE in extract_insn: unrecognizable insn
   Product: gcc
   Version: 15.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: target
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Bug found in SPEC CPU 2017 625.x264_s.

Reproducer (test.c):

int a;
void
c (char d[], char h[][0], char i[][4][4])
{
  for (int b; b < 2; b++)
for (int e = 0; e < 4; e++)
  for (int f = 0; f < 4; f++)
{
  int g = e - 1;
  if (d[e] || d[g])
i[b][e][f] = 2;
  else if (h[0][g] || a)
i[b][e][f] = 0;
}
}

Compile with:

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -c -Ofast test.c

Output:

test.c: In function 'c':
test.c:15:1: error: unrecognizable insn:
   15 | }
  | ^
(insn 1200 0 0 (parallel [
(set (reg:RVVMF4QI 749 [orig:240 vect__217.22 ] [240])
(unspec:RVVMF4QI [
(reg:DI 0 zero)
] UNSPEC_VUNDEF))
(clobber (scratch:DI))
]) -1
 (nil))
during RTL pass: reload
test.c:15:1: internal compiler error: in extract_insn, at recog.cc:2812
0xa95819 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
/home/jeremy/gittrees/rise-qemu/gcc/gcc/rtl-error.cc:108
0xa9583b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
/home/jeremy/gittrees/rise-qemu/gcc/gcc/rtl-error.cc:116
0xa94117 extract_insn(rtx_insn*)
/home/jeremy/gittrees/rise-qemu/gcc/gcc/recog.cc:2812
0x10db392 ira_remove_insn_scratches(rtx_insn*, bool, _IO_FILE*, rtx_def*
(*)(rtx_def*))
/home/jeremy/gittrees/rise-qemu/gcc/gcc/ira.cc:5381
0x111df4f remove_insn_scratches
/home/jeremy/gittrees/rise-qemu/gcc/gcc/lra.cc:2154
0x111df4f lra_emit_move(rtx_def*, rtx_def*)
/home/jeremy/gittrees/rise-qemu/gcc/gcc/lra.cc:513
0x112c143 match_reload
/home/jeremy/gittrees/rise-qemu/gcc/gcc/lra-constraints.cc:1184
0x11383a4 curr_insn_transform
/home/jeremy/gittrees/rise-qemu/gcc/gcc/lra-constraints.cc:4778
0x1139c8b lra_constraints(bool)
/home/jeremy/gittrees/rise-qemu/gcc/gcc/lra-constraints.cc:5481
0x1120a52 lra(_IO_FILE*, int)
/home/jeremy/gittrees/rise-qemu/gcc/gcc/lra.cc:2442
0x10d673f do_reload
/home/jeremy/gittrees/rise-qemu/gcc/gcc/ira.cc:5973
0x10d673f execute
/home/jeremy/gittrees/rise-qemu/gcc/gcc/ira.cc:6161
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
==

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/rise-qemu/install/libexec/gcc/riscv64-unknown-linux-gnu/15.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/rise-qemu/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/rise-qemu/install
--with-sysroot=/home/jeremy/gittrees/rise-qemu/install/sysroot
--with-pkgversion=gbb5f619a938-dirty --with-system-zlib --enable-shared
--enable-tls --enable-languages=c,c++,fortran --disable-libmudflap
--disable-libssp --disable-libquadmath --disable-libsanitizer --disable-nls
--disable-bootstrap --src=/home/jeremy/gittrees/rise-qemu/gcc --enable-multilib
--with-abi=lp64d --with-arch=rv64gc --with-tune= --with-isa-spec=20191213
'CFLAGS_FOR_TARGET=-O2-mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2   
-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 15.0.0 20240509 (experimental) (gbb5f619a938-dirty)

[Bug target/112651] RISC-V Vector new option -mvect-lmul required to force LMUL values (rather than --param=riscv-autovec-lmul to hint at values)

2023-11-21 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112651

Jeremy Bennett  changed:

   What|Removed |Added

Summary|RISC-V Vector   |RISC-V Vector new option
   |--param=riscv-autovec-lmul  |-mvect-lmul required to
   |should be -mvect-lmul   |force LMUL values (rather
   ||than
   ||--param=riscv-autovec-lmul
   ||to hint at values)

--- Comment #1 from Jeremy Bennett  ---
Updated, following the clarification in Bug 112648.

--param=riscv-autovec-lmul=

is intended as a hint to the optimizer, not as a mandate to only use a
particular LMUL value.

Therefore this bug covers an enhancement (-mvect-lmul) to support RISC-V Vector
processors which do not support all LMUL values.

It appears that the RISC-V vector standard requires all LMUL values to be
supported.  However the implementation of efficient LMUL != 1 on silicon is
very difficult leading at least one manufacturer to only support LMUL = 1.

As such this is an option, which should be default not be enabled, but should
be available where needed.

[Bug target/112648] RISC-V Vector parameter riscv-autovec-lmul value is ineffective

2023-11-21 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648

--- Comment #3 from Jeremy Bennett  ---
Following a discussion on the weekly call, it seems that I have misunderstood
the purpose of this parameter. It seems it is a hint to the optimizer that a
particular LMUL value is most efficient, not as a mandate to only use that LMUL
value.

I have raised Bug 112650 to update the GCC documentation for RISC-V parameters.
Once the behavior is confirmed, this bug can be closed.

I shall also update Bug 112651, since there is a need to force LMUL to
particular values for chips which do not implement all LMUL values.

[Bug target/112648] RISC-V Vector parameter riscv-autovec-lmul value is ineffective

2023-11-21 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648

--- Comment #2 from Jeremy Bennett  ---
Thanks Richard. Bug 112651 filed to capture this suggestion.

[Bug target/112651] New: RISC-V Vector --param=riscv-autovec-lmul should be -mvect-lmul

2023-11-21 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112651

Bug ID: 112651
   Summary: RISC-V Vector --param=riscv-autovec-lmul should be
-mvect-lmul
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: target
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

See the comment from Richard Biener in Bug 112648

"...using a --param for a correctness thing isn't recommended, I'd transition
that to -mvect-lmul=N..."

Filing this bug as a request for this change.

[Bug other/112650] New: RISC-V parameters are not documented

2023-11-21 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112650

Bug ID: 112650
   Summary: RISC-V parameters are not documented
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: other
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

GCC for RISC-V defines several parameters to control compilation:
- riscv-strcmp-inline-limit
- riscv-autovec-preference
- riscv-autovec-lmul
- riscv-vector-abi

The last of these is commented as an undocumented experimental switch in
riscv.opt

None of these parameters are included in the user manual (specifically in the
"RISC-V Options" section of invoke.texi).  While parameters often relate to
internal interfaces, and hence are unstable, they are still available to the
user, and should be documented accordingly.

The "Arm Options" section includes a good reference for such documentation,
including warning about the unstable nature of parameters.

[Bug target/112648] New: RISC-V Vector parameter riscv-autovec-lmul value is ineffective

2023-11-21 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112648

Bug ID: 112648
   Summary: RISC-V Vector parameter riscv-autovec-lmul value is
ineffective
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: target
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 56656
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56656=edit
Reproducer source

The GCC parameter riscv-autovec-lmul is used to force LMUL to be held to a
particular value. Vital for processors which do not support changing LMUL. The
parameter is not always effective.

Reproducer (test.c):

int a[8];
int b;
int c() {
  for (; b; b++)
a[b] = (float)b;
}

Compile with:

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -O2
--param=riscv-autovec-lmul=m1 -S test.c

Detect value of LMUL != m1 using grep:

grep 'vsetvli.*\(\(m8\)\|\(m4\)\|\(m2\)\|\(mf2\)\|\(mf4\)\|\(mf8\)\)' test.s

Output is:

vsetvli a4,a3,e8,mf4,ta,ma

System information
==

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g41aacdea55c --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20231121 (experimental) (g41aacdea55c)

[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

2023-10-03 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #7 from Jeremy Bennett  ---
I can confirm this is resolved, and also that SPEC CPU 2017 627.cam4_s compiles
successfully.

Thanks for the patch. Marking as resolved.

[Bug middle-end/111548] RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

2023-10-03 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548

Jeremy Bennett  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Jeremy Bennett  ---
Confirmed that the test now passes, as indeed does SPEC CPU 2017 602.gcc_s.

Thanks for the fix. Marking as resolved.

[Bug middle-end/111566] New: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)

2023-09-24 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566

Bug ID: 111566
   Summary: RISC-V Vector Fortran: ICE in final_scan_insn_1 (final
RTL pass)
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55979
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55979=edit
Reproducer

Issue discovered with the SPEC CPU 2017 627.cam4_s benchmark. It appears to be
an interaction between RISC-V vector and the -fmax-stack-var-size parameter.

Reproducer (test.f90)

module a
  integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
end module a
module b
  use a,  c => shr_kind_r8
contains
  subroutine d(cg , km, i1, i2)
real (c) ch(i2,km)
real (c) cg(4,i1:i2,km)
real  dc(i2,km)
real(c) ci(i2,km)
real(c) cj(i2,km)
do k=2,ck
   do i=i1,0
  cl = ci(i,k) *ci(i,1) /  cj(i,k)+ch(i,1)
  cm = cg(1,i,k) - min(e,cg(1,i,co))
  dc(i,k) = sign(cm, cl)
   enddo
enddo
if ( cq == 0 ) then
   do i=i1,i2
  if( cr <=  cs ) then
 cg= sign( min(ct,   cg),  cg)
  endif
   enddo
endif
  end subroutine d
end module b

Compile with:

riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d -c -Ofast
-ftree-vectorize --param=riscv-autovec-preference=scalable
-fallow-argument-mismatch -fmax-stack-var-size=65536 test.f90

Output is:

   27 |   end subroutine d
  |  ^
Error: could not split insn
(insn 967 168 1115 (set (mem/c:V16DI (plus:DI (reg/f:DI 2 sp)
(const_int 128 [0x80])) [4 %sfp+[-1024, -16] S128 A128])
(mem/c:V16DI (reg/f:DI 2 sp) [4 %sfp+[-1152, -16] S128 A128]))
"test.f90":16:44 1117 {*movv16di_mem_to_mem}
 (nil))
during RTL pass: final
test.f90:27:18: internal compiler error: in final_scan_insn_1, at final.cc:2808
0x9d3f63 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
/home/jeremy/gittrees/mustang/gcc/gcc/rtl-error.cc:108
0x965949 final_scan_insn_1
/home/jeremy/gittrees/mustang/gcc/gcc/final.cc:2808
0xe952af final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*)
/home/jeremy/gittrees/mustang/gcc/gcc/final.cc:2887
0xe954f4 final_1
/home/jeremy/gittrees/mustang/gcc/gcc/final.cc:1979
0xe9601a rest_of_handle_final
/home/jeremy/gittrees/mustang/gcc/gcc/final.cc:4240
0xe9601a execute
/home/jeremy/gittrees/mustang/gcc/gcc/final.cc:4318
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
==

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g59d27cc55a0 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230923 (experimental) (g59d27cc55a0)

[Bug middle-end/111548] New: RISC-V Vector: ICE in validate_change_or_fail (vsetvl pass)

2023-09-23 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111548

Bug ID: 111548
   Summary: RISC-V Vector: ICE in validate_change_or_fail (vsetvl
pass)
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55973
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55973=edit
Reproducer source code

This issue was identified building SPEC CPU 2017 602.gcc_s.

Reproducer (test.c):

a, c, d;
*b;
h() {
  int e;
  i();
  for (;;) {
unsigned f;
char *g;
f = a;
for (; f; f--) {
  if (*g == '"')
e = !e;
  *b = g++;
}
if (c)
  break;
f = d;
for (; d;)
  if (e)
b++;
  }
}

Compile with:

riscv64-unknown-linux-gnu-gcc -w -march=rv64gcv -mabi=lp64d -c -Ofast \
-ftree-vectorize --param=riscv-autovec-preference=scalable test.c

Output is:
during RTL pass: vsetvl
test.c: In function 'h':
test.c:22:1: internal compiler error: in validate_change_or_fail, at
config/riscv/riscv-vsetvl.cc:788
   22 | }
  | ^
0xa6ef0b validate_change_or_fail
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:788
0xa6f0bb validate_change_or_fail
/home/jeremy/gittrees/mustang/gcc/gcc/hash-set.h:64
0xa6f0bb change_insn
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:804
0x165d292 pass_vsetvl::earliest_fusion()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3415
0x165da61 pass_vsetvl::vsetvl_fusion()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3457
0x165f950 pass_vsetvl::lazy_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4373
0x165fad1 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4413
0x165fad1 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4394
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
==

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g59d27cc55a0 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230923 (experimental) (g59d27cc55a0)

[Bug middle-end/111395] RISC-V Vector Fortran: ICE in get_avl_or_vl_reg (vsetvl pass)

2023-09-19 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #2 from Jeremy Bennett  ---
I can confirm this issue is resolved. Thanks.

[Bug middle-end/111391] RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass

2023-09-19 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #2 from Jeremy Bennett  ---
Confirm this issue is now resolved. Thanks.

[Bug middle-end/111395] New: RISC-V Vector Fortran: ICE in get_avl_or_vl_reg (vsetvl pass)

2023-09-12 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395

Bug ID: 111395
   Summary: RISC-V Vector Fortran: ICE in get_avl_or_vl_reg
(vsetvl pass)
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55887
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55887=edit
Reproducer

Found because of failure of SPEC CPU 2017 621_wrf_s to compile.

This appears to be related to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=11137, which is now resolved.

Reproducer (test.f90):

MODULE a
  REAL b
CONTAINS
  SUBROUTINE c(d,KTE)
REAL,DIMENSION(KTE) :: d,e,f,g
REAL,DIMENSION(KTE) :: h
i : DO j=1,b
   z=k
   DO l=m,n
  IF(o>=p)THEN
 IF(laf)THEN
   DO l=m,n
  d=h
   ENDDO
ENDIF
  END SUBROUTINE c
END MODULE a

Compile with:

riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d -c -Ofast \
-ftree-vectorize --param=riscv-autovec-preference=scalable test.f90

Output:

during RTL pass: vsetvl
test.f90:37:18:

   37 |   END SUBROUTINE c
  |  ^
internal compiler error: in get_avl_or_vl_reg, at
config/riscv/riscv-vsetvl.cc:2297
0x9a24e5 riscv_vector::vector_insn_info::get_avl_or_vl_reg() const
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:2297
0x9a24e5 riscv_vector::vector_insn_info::get_avl_or_vl_reg() const
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:2271
0x16102f7 insert_vsetvl
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:724
0x1610edd pass_vsetvl::commit_vsetvls()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3615
0x1611191 pass_vsetvl::pre_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3728
0x1611ed8 pass_vsetvl::lazy_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4360
0x1612031 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4395
0x1612031 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4376
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g35f498d8dfc --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230912 (experimental) (g35f498d8dfc) 

Tool chain built with component commits:

Repository   SHA-1 hash (commit ID)  
--   --  
gcc  35f498d8dfc8e579eaba2ff2d2b96769c632fd58
binutils-gdb 318d3bda5cad124bd11eebb0349d0f183ba625b1
glibc073edbdfabaad4786e974a451efe4b6b3f7a5a61

[Bug middle-end/111391] New: RISC-V Vector: ICE in lra_split_hard_reg_for during reload pass

2023-09-12 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111391

Bug ID: 111391
   Summary: RISC-V Vector: ICE in lra_split_hard_reg_for during
reload pass
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55885
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55885=edit
Reproducer

This looks like a reappearance of
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296.  Found when investigating
failure of SPEC CPU 2017 600_perlbench_s to compile.

Reproducer (test.c)

int d ();
typedef struct
{
  int b;
} c;
int
e (char *f, long g)
{
  f += g;
  while (g--)
*--f = d;
}

int
d (c * f)
{
  while (h ())
switch (f->b)
  case 'Q':
  {
long a;
e (, sizeof (a));
i (a);
  }
}

Compile with:

riscv64-unknown-linux-gnu-gcc -Wno-int-conversion -Wno-implicit-function \
-Wno-incompatible-pointer-types -Wno-implicit-function-declaration \
-march=rv64gcv -mabi=lp64d -c -Ofast -ftree-vectorize \
--param=riscv-autovec-preference=scalable test.c

Output is:


test.c: In function 'd':
test.c:25:1: error: unable to find a register to spill
   25 | }
  | ^
test.c:25:1: error: this is the insn:
(insn 49 48 58 5 (set (subreg:V8QI (reg:DI 158) 0)
(if_then_else:V8QI (unspec:V8BI [
(const_vector:V8BI [
(const_int 1 [0x1]) repeated x8
])
(const_int 8 [0x8])
(const_int 2 [0x2]) repeated x2
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(vec_duplicate:V8QI (reg:QI 155))
(unspec:V8QI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "test.c":23:2 1450 {*pred_broadcastv8qi}
 (expr_list:REG_DEAD (reg:QI 155)
(expr_list:REG_DEAD (reg:SI 67 vtype)
(expr_list:REG_DEAD (reg:SI 66 vl)
(expr_list:REG_DEAD (reg:SI 0 zero)
(nil))
during RTL pass: reload
test.c:25:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1861
0x904fbb _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
/home/jeremy/gittrees/mustang/gcc/gcc/rtl-error.cc:108
0xf35590 lra_split_hard_reg_for()
/home/jeremy/gittrees/mustang/gcc/gcc/lra-assigns.cc:1861
0xf2f205 lra(_IO_FILE*)
/home/jeremy/gittrees/mustang/gcc/gcc/lra.cc:2495
0xee6519 do_reload
/home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:5970
0xee6519 execute
/home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:6156
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g35f498d8dfc --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230912 (experimental) (g35f498d8dfc)

[Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

2023-09-12 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375

Jeremy Bennett  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Jeremy Bennett  ---
Thanks @JuzheZhong,

I have tried again with the latest GCC and the problem has gone away.  This can
now be marked as fixed.

[Bug middle-end/111375] RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

2023-09-12 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375

--- Comment #2 from Jeremy Bennett  ---
(In reply to JuzheZhong from comment #1)
> I can't reproduce the ICE in your testcase with same command.
> 
> ~/work/toolchain/develop/build/dev-rv64gcv_zfh-lp64d-medany-linux-spike/
> install/bin/riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d
> -c -Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable bug.f90
> 
> 
> No ICE.
> 
> Could you help me with that ?

Hi  JuzheZhong

I built with the following components:

Repository   SHA-1 hash (commit ID)  
--   --  
gcc  316d57da5bb9205b946afc56d78582fee874e4b5
binutils-gdb 9a343d2bb57c4555dedad9b43907aeeda7b51dae
glibc073edbdfabaad4786e974a451efe4b6b3f7a5a61

Is this the same as you? I'll do a clean rebuild with the latest tool chain in
case this problem has been fixed.

[Bug middle-end/111375] New: RISC-V vector Fortran: SEGV ICE during get_avl_or_vl_reg (vsetvl pass)

2023-09-11 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111375

Bug ID: 111375
   Summary: RISC-V vector Fortran: SEGV ICE during
get_avl_or_vl_reg (vsetvl pass)
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55878
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55878=edit
Test case for the issue

Found when building SPEC CPU 2017 621.wrf_s.  The same problem appears to occur
in 627.cam4_s and 628.pop2_s

Reproducer (test.f90):

MODULE a
CONTAINS
  SUBROUTINE b(KTE)
REAL,DIMENSION(KTE) :: c,e,f,q
LOGICAL ae
DO af=ag,ah
   DO i=ai,aj
  CALL ak(al,i,af,am,an,d,g,c,q,e,f,h,r   &
   ,e,f,s,ao,LTOP,ap,aq,ar,as,at,au,av,aw &
   ,ae,ax,ay,az,ba,bb,bc  &
   ,d,be,bf,bg,bh,bi,ai,aj,ag,ah,KTS,KTE)
   ENDDO
ENDDO
  END SUBROUTINE b
  SUBROUTINE ak(al,i,af,am,an,bj,bk   &
   ,bl,bm,bn,t,h,u,e,f,s,ao,LTOP,ap   &
   ,aq,ar,as,at,au,av,aw,ae   &
   ,ax,a,b,c,d,bc &
   ,bd,be,bf,bg,bh,bi,ai,aj,ag,ah,KTS,KTE)
REAL,DIMENSION(:) :: bl,bm,bn,t
REAL,DIMENSION(:) :: e,f
REAL,DIMENSION(KTE) :: v
LOGICAL ae
l : DO j=1,w
   DO k=LTOP,m
  IF(o>=p)THEN
 n=x()
  ENDIF
   ENDDO
   y : DO z=1,2
  DO k=LTOP,m
 aa=v(k)+aa
  ENDDO
  ab=aa
  DO k=KTS,m
 IF(k<=ac)ad=k
  ENDDO
  IF(LCOR<=ad)THEN
 DO k=LCOR,ad
v=ab
 ENDDO
  ENDIF
   ENDDO  y
ENDDO  l
  END SUBROUTINE ak
END MODULE a

Compile with:

riscv64-unknown-linux-gnu-gfortran -w -march=rv64gcv -mabi=lp64d -c -Ofast
-ftree-vectorize --param=riscv-autovec-preference=scalable test.f90

Output is:

during RTL pass: vsetvl
test.f90:14:18:

   14 |   END SUBROUTINE b
  |  ^
internal compiler error: in get_avl_or_vl_reg, at
config/riscv/riscv-vsetvl.cc:2297
0x98b1e3 riscv_vector::vector_insn_info::get_avl_or_vl_reg() const
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:2297
0x98b1e3 riscv_vector::vector_insn_info::get_avl_or_vl_reg() const
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:2271
0x15f8d27 insert_vsetvl
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:724
0x15f990d pass_vsetvl::commit_vsetvls()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3615
0x15f9bc1 pass_vsetvl::pre_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3728
0x15fa908 pass_vsetvl::lazy_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4358
0x15faa11 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4393
0x15faa11 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4374
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
==

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=gf3ba57163ce --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230908 (experimental) (gf3ba57163ce)

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

2023-09-08 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

Jeremy Bennett  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Jeremy Bennett  ---
I can confirm this patch resolves the issue.

[Bug target/111295] RISC-V vector ICE in vsetvl pass

2023-09-08 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #7 from Jeremy Bennett  ---
I can confirm this patch resolves the issue.

[Bug target/111295] RISC-V vector ICE in vsetvl pass

2023-09-06 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295

--- Comment #4 from Jeremy Bennett  ---
@JuzheZhong  - it's a C test case, not C++.  Look like you are trying to
compile it as C++.

[Bug target/111295] RISC-V vector ICE in vsetvl pass

2023-09-05 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295

--- Comment #1 from Jeremy Bennett  ---
Further analysis suggests this also causes the following SPEC CPU 2017
benchmarks to fail: 602.gcc_s, 648.exchange2_s, 607.cactuBSSN_s, 621.wrf_s,
627.cam4_s, 628.pop2_s, 638.imagick_s, 649.fotonik3d_s and 654.roms_s

[Bug middle-end/111296] RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

2023-09-05 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

--- Comment #1 from Jeremy Bennett  ---
Created attachment 55844
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55844=edit
Testcase (test.cpp)

[Bug middle-end/111296] New: RISC-V vector: ICE in lra_split_hard_reg_for during reload pass

2023-09-05 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111296

Bug ID: 111296
   Summary: RISC-V vector: ICE in lra_split_hard_reg_for during
reload pass
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

The following issue was identified while attempting to compile SPEC CPU 2017
641.leela_s benchmark.

Reproducer (test.cc):

struct a
{
  int b;
  int c;
};
int d;
a
e ()
{
  a f;
  int g = d - 1, h = d / 2 - 1;
  f.b = g;
  f.c = h;
  return f;
}

Compiled with:

riscv64-unknown-linux-gnu-g++ -std=c++03 -march=rv64gcv -mabi=lp64d -c \
-Ofast -ftree-vectorize --param=riscv-autovec-preference=scalable \
test.cpp

Output is:

test.cpp: In function 'a e()':
test.cpp:15:1: error: unable to find a register to spill
   15 | }
  | ^
test.cpp:15:1: error: this is the insn:
(insn 59 69 68 2 (set (subreg:V2SI (reg:DI 181) 0)
(if_then_else:V2SI (unspec:V2BI [
(const_vector:V2BI [
(const_int 1 [0x1]) repeated x2
])
(const_int 2 [0x2]) repeated x3
(const_int 0 [0])
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(plus:V2SI (reg:V2SI 182 [141])
(const_vector:V2SI [
(const_int -1 [0x]) repeated x2
]))
(unspec:V2SI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF))) "test.cpp":15:1 3122 {pred_addv2si}
 (expr_list:REG_DEAD (reg:V2SI 182 [141])
(expr_list:REG_DEAD (reg:SI 67 vtype)
(expr_list:REG_DEAD (reg:SI 66 vl)
(expr_list:REG_DEAD (reg:SI 0 zero)
(nil))
during RTL pass: reload
test.cpp:15:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1861
0x9bab61 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
/home/jeremy/gittrees/mustang/gcc/gcc/rtl-error.cc:108
0x1203e80 lra_split_hard_reg_for()
/home/jeremy/gittrees/mustang/gcc/gcc/lra-assigns.cc:1861
0x11fdaf5 lra(_IO_FILE*)
/home/jeremy/gittrees/mustang/gcc/gcc/lra.cc:2495
0x11b4dd9 do_reload
/home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:5970
0x11b4dd9 execute
/home/jeremy/gittrees/mustang/gcc/gcc/ira.cc:6156
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.


System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g8451fbd5687 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230904 (experimental) (g8451fbd5687)

[Bug middle-end/111295] New: RISC-V vector ICE in vsetvl pass

2023-09-05 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111295

Bug ID: 111295
   Summary: RISC-V vector ICE in vsetvl pass
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55843
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55843=edit
Test case

The following issue was identified while attempting to compile SPEC CPU 2017
600.perlbench_s benchmark.

Reproducer (test.c):

int a, b, c, e, f, g, h, i, j, k;
long l;
int q ()
{
  int r ();
  char *o, *d;
  _Bool p = f;
  while (g)
{
  int m, n;
  for (; m <= n; m++)
*d++ = m;
  k = 1;
  if (e)
break;
  switch (*o)
{
case 'N':
  o++;
  if (c)
if (h)
  while (i)
{
  s (-l, ~0);
  t (j);
  d = d + (a & 1000 ? u (r, 2) : b);
}
}
  if (*o)
p ? s () : 0;
}
}

This is compiled with:

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -c \
-Wno-implicit-function-declaration -Ofast \
-ftree-vectorize --param=riscv-autovec-preference=scalable test.c

The output is:

during RTL pass: vsetvl
test.c: In function 'q':
test.c:32:1: internal compiler error: Segmentation fault
   32 | }
  | ^
0x10db7d3 crash_signal
/home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:314
0x7fc85743c4af ???
./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x1548f8a riscv_vector::vector_insn_info::get_avl_reg_rtx() const
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.h:339
0x1548f8a insert_vsetvl
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:750
0x1549a5d pass_vsetvl::commit_vsetvls()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3642
0x1549d11 pass_vsetvl::pre_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:3755
0x154b988 pass_vsetvl::lazy_vsetvl()
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4442
0x154ba91 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4477
0x154ba91 pass_vsetvl::execute(function*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-vsetvl.cc:4458
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g8451fbd5687 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230904 (experimental) (g8451fbd5687)

[Bug fortran/110996] RISC-V vector Fortran: SEGV ICE during parsing

2023-08-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110996

--- Comment #3 from Jeremy Bennett  ---
@JuzheZhong I believe this is in someway related to RVV.  If I remove `v' from
the march:

riscv64-unknown-linux-gnu-gfortran -march=rv64gc -mabi=lp64d -c -Ofast
testcase.f90

The output I get is correct:

testcase.f90:6:20:

6 |SUBROUTINE c(d) e
  |1
Error: Syntax error in SUBROUTINE statement at (1)

Why does adding `v' to the -march string cause a SEGV?

[Bug middle-end/110994] RISC-V Fortran: Illegal instruction ICE with scalable autovec

2023-08-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #3 from Jeremy Bennett  ---
Confirmed the patch resolves this issue, and the code correctly produces a
syntax error.

[Bug middle-end/110989] RISC-V vector ICE due to invalid tree code in GIMPLE vect pass

2023-08-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110989

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #4 from Jeremy Bennett  ---
Confirmed the patch resolves this issue.

[Bug target/110964] RISC-V vector ICE in expand_cond_len_ternop

2023-08-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110964

Jeremy Bennett  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #2 from Jeremy Bennett  ---
Confirmed the patch resolves this issue.

[Bug middle-end/110962] RISC-V vector Fortran ICE in expand_expr_real_2

2023-08-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110962

Jeremy Bennett  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #2 from Jeremy Bennett  ---
Confirmed patch resolves the issue.

[Bug target/110950] RISC-V vector ICE in expand_const_vector

2023-08-14 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

Jeremy Bennett  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #5 from Jeremy Bennett  ---
Patch resolves the issue.

[Bug fortran/110996] New: RISC-V vector Fortran: SEGV ICE during parsing

2023-08-11 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110996

Bug ID: 110996
   Summary: RISC-V vector Fortran: SEGV ICE during parsing
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: fortran
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55726
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55726=edit
Fortran 90 source code for the test case

This appears to be a failure in the Fortran parser, which only occurs if the
RISC-V vector ISA extension is specified.

This is the reproducer (testcase.f90):

  CONTAINS
   SUBROUTINE a
   END
   SUBROUTINE b
   END
   SUBROUTINE c(d) e
SUBROUTINE f
  END
END

(which has a syntax error with the stray "e" at the end of the declaration of
"SUBROUTINE c").

This is compiled with:

riscv64-unknown-linux-gnu-gfortran -march=rv64gcv -mabi=lp64d -c \
-Ofast testcase.f90

NOTE. The error only occurs if the "v" extensions is specified in the "-march"
string.

The output is:

testcase.f90:6:20:

6 |SUBROUTINE c(d) e
  |1
Error: Syntax error in SUBROUTINE statement at (1)
f951: internal compiler error: Segmentation fault
0x112a263 crash_signal
/home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:314
0x7fdd1203c4af ???
./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0xaaea0a resolve_symbol
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/resolve.cc:16643
0xadadc2 do_traverse_symtree
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/symbol.cc:4190
0xab95ed resolve_types
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/resolve.cc:17963
0xab9697 resolve_types
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/resolve.cc:17977
0xac08ec gfc_resolve(gfc_namespace*)
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/resolve.cc:18083
0xa9f250 resolve_all_program_units
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/parse.cc:6909
0xa9f250 gfc_parse_file()
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/parse.cc:7165
0xaf3533 gfc_be_parse_file
/home/jeremy/gittrees/mustang/gcc/gcc/fortran/f95-lang.cc:229
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g68783211f66 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230811 (experimental) (g68783211f66)

[Bug middle-end/110994] New: RISC-V Fortran: Illegal instruction ICE with scalable autovec

2023-08-11 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

Bug ID: 110994
   Summary: RISC-V Fortran: Illegal instruction ICE with scalable
autovec
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55723
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55723=edit
Fortran 90 source code of the test case

Discovered by accident when hunting down a RVV bug, but this appears to be
connected with the autovectorizer generically rather than specifically the
RISC-V vector ISA extension.

The following code (testcase.f90) causes an ICE when using RISC-V as target
with
--param=riscv-autovec-preference=scalable.

SUBROUTINE d(e) f

(this is invalid Fortran 90, but it should still not trigger an ICE)

Compiled with:

riscv64-unknown-linux-gnu-gfortran -march=rv64gc -mabi=lp64d -c \
-Ofast --param=riscv-autovec-preference=scalable testcase.f90

Output is:

f951: internal compiler error: Illegal instruction
0x112a263 crash_signal
/home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:314
0x7f0d57e3c4af ???
./signal/../sysdeps/unix/sysv/linux/x86_64/libc_sigaction.c:0
0x9342a9 poly_int_pod<2u, unsigned short>::to_constant() const
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv.cc:6565
0x9342a9 riscv_hard_regno_nregs
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv.cc:6578
0x1092519 init_reg_modes_target()
/home/jeremy/gittrees/mustang/gcc/gcc/reginfo.cc:466
0xd00827 init_emit_regs()
/home/jeremy/gittrees/mustang/gcc/gcc/emit-rtl.cc:6072
0x9e6058 backend_init
/home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:1749
0x9e6058 do_compile
/home/jeremy/gittrees/mustang/gcc/gcc/toplev.cc:2108
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g68783211f66 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230811 (experimental) (g68783211f66)

[Bug middle-end/110989] New: RISC-V vector ICE due to invalid tree code in GIMPLE vect pass

2023-08-11 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110989

Bug ID: 110989
   Summary: RISC-V vector ICE due to invalid tree code in GIMPLE
vect pass
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55722
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55722=edit
C source of the testcase

The following code (testcase.c) causes an ICE when using RISC-V vector as
target.

int a, b, c;
double *d;
void e() {
  double f;
  for (; c; c++, d--)
f = *d ?: *( + c);
  b = f;
}

Compiled with:

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -c \
-Ofast --param=riscv-autovec-preference=scalable testcase.c

The output is:

during GIMPLE pass: vect
testcase.c: In function 'e':
testcase.c:3:6: internal compiler error: tree check: expected class 'type',
have 'exceptional' () in build_int_cst, at tree.cc:1507
3 | void e() {
  |  ^
0x914c99 tree_class_check_failed(tree_node const*, tree_code_class, char
const*, int, char const*)
/home/jeremy/gittrees/mustang/gcc/gcc/tree.cc:8949
0x91e2c7 tree_class_check(tree_node*, tree_code_class, char const*, int, char
const*)
/home/jeremy/gittrees/mustang/gcc/gcc/tree.h:3700
0x91e2c7 build_int_cst(tree_node*, poly_int<2u, long>)
/home/jeremy/gittrees/mustang/gcc/gcc/tree.cc:1507
0x20f3e2d vectorizable_load
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vect-stmts.cc:10719
0x2100ee5 vect_transform_stmt(vec_info*, _stmt_vec_info*,
gimple_stmt_iterator*, _slp_tree*, _slp_instance*)
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vect-stmts.cc:12337
0x131f464 vect_transform_loop_stmt
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vect-loop.cc:11039
0x13442bc vect_transform_loop(_loop_vec_info*, gimple*)
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vect-loop.cc:11488
0x138611f vect_transform_loops
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vectorizer.cc:1004
0x138679c try_vectorize_loop_1
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vectorizer.cc:1150
0x138679c try_vectorize_loop
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vectorizer.cc:1180
0x1386b44 execute
/home/jeremy/gittrees/mustang/gcc/gcc/tree-vectorizer.cc:1296
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g68783211f66 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230811 (experimental) (g68783211f66)

[Bug middle-end/110964] New: RISC-V vector ICE in expand_cond_len_ternop

2023-08-09 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110964

Bug ID: 110964
   Summary: RISC-V vector ICE in expand_cond_len_ternop
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55713
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55713=edit
C source code of the bug reproducer

The following code (testcase.c) causes an ICE when using RISC-V vector as
target.

int *a;
long b, c;

int d ()
{
  const int e;
  for (; a < e; a++)
c += *a * b;
}

Compiled with:

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d -c \
-Ofast --param=riscv-autovec-preference=scalable testcase.c

Output is:

testcase.c: In function 'd':
testcase.c:7:12: warning: comparison between pointer and integer
7 |   for (; a < e; a++)
  |^
during RTL pass: expand
testcase.c:8:7: internal compiler error: in expand_cond_len_ternop, at
config/riscv/riscv-v.cc:3579
8 | c += *a * b;
  |   ^~
0x93b0f3 riscv_vector::expand_cond_len_ternop(unsigned int, rtx_def**)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3579
0x1be5b61 gen_cond_len_fmarvvm1di(rtx_def*, rtx_def*, rtx_def*, rtx_def*,
rtx_def*, rtx_def*, rtx_def*, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/autovec.md:1644
0xf41dd2 rtx_insn* insn_gen_fn::operator()(rtx_def*, rtx_def*, rtx_def*,
rtx_def*, rtx_def*, rtx_def*, rtx_def*, rtx_def*) const
/home/jeremy/gittrees/mustang/gcc/gcc/recog.h:411
0xf41dd2 maybe_gen_insn(insn_code, unsigned int, expand_operand*)
/home/jeremy/gittrees/mustang/gcc/gcc/optabs.cc:8237
0xf463cc maybe_expand_insn(insn_code, unsigned int, expand_operand*)
/home/jeremy/gittrees/mustang/gcc/gcc/optabs.cc:8265
0xf463cc expand_insn(insn_code, unsigned int, expand_operand*)
/home/jeremy/gittrees/mustang/gcc/gcc/optabs.cc:8296
0xdc6de0 expand_fn_using_insn
/home/jeremy/gittrees/mustang/gcc/gcc/internal-fn.cc:255
0xb72dbf expand_call_stmt
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:2737
0xb72dbf expand_gimple_stmt_1
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:3880
0xb72dbf expand_gimple_stmt
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:4044
0xb77bc6 expand_gimple_basic_block
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:6096
0xb79576 execute
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:6831
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g5c27c911f6b --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230809 (experimental) (g5c27c911f6b)

[Bug middle-end/110962] New: RISC-V vector Fortran ICE in expand_expr_real_2

2023-08-09 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110962

Bug ID: 110962
   Summary: RISC-V vector Fortran ICE in expand_expr_real_2
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55712
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55712=edit
Fortran source for test case

The following code (testcase.f90) causes an ICE when using RISC-V vector as
target.

SUBROUTINE a(b,c,d)
  LOGICAL,DIMENSION(INOUT)  :: b
  LOGICAL e
  REAL, DIMENSION(IN) ::  c
  REAL, DIMENSION(INOUT)  ::  d
  REAL, DIMENSION(SIZE(c))   :: f
  WHERE (b.AND.e)
 WHERE (f>=0.)
d = g
 ENDWHERE
  ENDWHERE
END SUBROUTINE a

Compiled with:

riscv64-unknown-linux-gnu-gfortran -march=rv64gcv -mabi=lp64d \
   -c -Ofast --param=riscv-autovec-preference=scalable testcase.f90

Output is:

during RTL pass: expand
testcase.f90:1:12:

1 | SUBROUTINE a(b,c,d)
  |^
internal compiler error: in expand_expr_real_2, at expr.cc:10566
0x830f6d expand_expr_real_2(separate_ops*, rtx_def*, machine_mode,
expand_modifier)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10566
0xc04ab0 expand_gimple_stmt_1
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:3983
0xc04ab0 expand_gimple_stmt
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:4044
0xc097c6 expand_gimple_basic_block
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:6096
0xc0b176 execute
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:6831
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=riscv64-unknown-linux-gnu-gfortran
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=g5c27c911f6b --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany' 'CXXFLAGS_FOR_TARGET=-O2-mcmodel=medany'
Thread model: posix
Supported LTO compression algorithms: zlib
gcc version 14.0.0 20230809 (experimental) (g5c27c911f6b)

[Bug middle-end/110950] RISC-V vector ICE in expand_const_vector

2023-08-08 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

--- Comment #1 from Jeremy Bennett  ---
Created attachment 55709
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55709=edit
Script to run the compilation

[Bug middle-end/110950] New: RISC-V vector ICE in expand_const_vector

2023-08-08 Thread jeremy.bennett at embecosm dot com via Gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

Bug ID: 110950
   Summary: RISC-V vector ICE in expand_const_vector
   Product: gcc
   Version: 14.0
Status: UNCONFIRMED
  Severity: normal
  Priority: P3
 Component: middle-end
  Assignee: unassigned at gcc dot gnu.org
  Reporter: jeremy.bennett at embecosm dot com
  Target Milestone: ---

Created attachment 55708
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=55708=edit
C source

The following code (testcase.c) causes an ICE when using RISC-V vector as
target.

a;
b() {
  long *c = 0;
  int *d;
  for (; a; ++a)
c[a] = d[-a];
}

Compiled with

riscv64-unknown-linux-gnu-gcc -march=rv64gcv -mabi=lp64d \
  -c -Ofast --param=riscv-autovec-preference=scalable \
  testcase.c

Output is

testcase.c:1:1: warning: data definition has no type or storage class
1 | a;
  | ^
testcase.c:1:1: warning: type defaults to 'int' in declaration of 'a'
[-Wimplicit-int]
testcase.c:2:1: warning: return type defaults to 'int' [-Wimplicit-int]
2 | b() {
  | ^
during RTL pass: expand
testcase.c: In function 'b':
testcase.c:6:10: internal compiler error: in expand_const_vector, at
config/riscv/riscv-v.cc:1510
6 | c[a] = d[-a];
  | ~^~~
0x8e70b6 expand_const_vector
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:1510
0x14a4df4 riscv_vector::legitimize_move(rtx_def*, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:1524
0x184044f gen_movrvvm8qi(rtx_def*, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/vector.md:1054
0xc56b57 rtx_insn* insn_gen_fn::operator()(rtx_def*,
rtx_def*) const
/home/jeremy/gittrees/mustang/gcc/gcc/recog.h:407
0xc56b57 emit_move_insn_1(rtx_def*, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:4164
0xc56f65 emit_move_insn(rtx_def*, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:4334
0xc2c4cd force_reg(machine_mode, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/explow.cc:693
0x14a2cee shuffle_generic_patterns
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3120
0x14a2cee expand_vec_perm_const_1
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3151
0x14a32b3 riscv_vector::expand_vec_perm_const(machine_mode, machine_mode,
rtx_def*, rtx_def*, rtx_def*, vec_perm_indices const&)
/home/jeremy/gittrees/mustang/gcc/gcc/config/riscv/riscv-v.cc:3203
0xefe0ce expand_vec_perm_const(machine_mode, rtx_def*, rtx_def*,
int_vector_builder > const&, machine_mode, rtx_def*)
/home/jeremy/gittrees/mustang/gcc/gcc/optabs.cc:6508
0xc4f682 expand_expr_real_2(separate_ops*, rtx_def*, machine_mode,
expand_modifier)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10453
0xc53c58 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10805
0xc4cb7a expand_expr_real(tree_node*, rtx_def*, machine_mode, expand_modifier,
rtx_def**, bool)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:9010
0xc4cb7a expand_expr(tree_node*, rtx_def*, machine_mode, expand_modifier)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.h:310
0xc4cb7a expand_expr_real_2(separate_ops*, rtx_def*, machine_mode,
expand_modifier)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:9345
0xc53c58 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:10805
0xc6062d store_expr(tree_node*, rtx_def*, int, bool, bool)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:6325
0xc62201 expand_assignment(tree_node*, tree_node*, bool)
/home/jeremy/gittrees/mustang/gcc/gcc/expr.cc:6043
0xb1f05c expand_gimple_stmt_1
/home/jeremy/gittrees/mustang/gcc/gcc/cfgexpand.cc:3946
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

System information
--

Using built-in specs.
COLLECT_GCC=./riscv64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/home/jeremy/gittrees/mustang/install/libexec/gcc/riscv64-unknown-linux-gnu/14.0.0/lto-wrapper
Target: riscv64-unknown-linux-gnu
Configured with: /home/jeremy/gittrees/mustang/gcc/configure
--target=riscv64-unknown-linux-gnu
--prefix=/home/jeremy/gittrees/mustang/install
--with-sysroot=/home/jeremy/gittrees/mustang/install/sysroot
--with-pkgversion=gf9d93f8cc24 --with-system-zlib --enable-shared --enable-tls
--enable-languages=c,c++,fortran --disable-libmudflap --disable-libssp
--disable-libquadmath --disable-libsanitizer --disable-nls --disable-bootstrap
--src=/home/jeremy/gittrees/mustang/gcc --enable-multilib --with-abi=lp64d
--with-arch=rv64gc --with-tune= --with-isa-spec=20191213 'CFLAGS_FOR_TARGET=-O2
   -mcmodel=medany'

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