[Bug c/113715] New: RISC-V: If the Zcmp is enabled, the a0 register operates abnormally when the program returns
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113715
Bug ID: 113715
Summary: RISC-V: If the Zcmp is enabled, the a0 register
operates abnormally when the program returns
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: mumuxi_ll at outlook dot com
Target Milestone: ---
When compiling the following test.c code with the options
-march=rv32ima_zca_zcb_zcmp_zcmt -mabi=ilp32 -Os, a bug appears when gcc
enables zcmp. In the disassembly dump.txt, it can be observed that when
executing the bne instruction in test_err, a0 is not set to 0 as the function
return value.
Source code:
void test_1(int onoff)
{
for (volatile int i = 0; i < 100; i ++) {
}
}
int test_err(void *param, int mode, int *saveAddr)
{
if (mode == 2) {
test_1(1);
}
return 0;
}
int main()
{
int ret = test_err((void *)0x123456, 3, (int *)0x123456);
for (volatile int i = ret; i < 100; i ++) {
ret = i * i;
}
return ret;
}
GCC ASM:
test_1:
addisp,sp,-16
sw zero,12(sp)
li a4,99
.L2:
lw a5,12(sp)
ble a5,a4,.L3
addisp,sp,16
jr ra
.L3:
lw a5,12(sp)
addia5,a5,1
sw a5,12(sp)
j .L2
test_err:
li a5,2
bne a1,a5,.L8
li a0,1
cm.push {ra}, -16
calltest_1
cm.popretz {ra}, 16
.L8:
ret
main:
addisp,sp,-16
sw zero,12(sp)
li a0,0
li a3,99
.L12:
lw a5,12(sp)
ble a5,a3,.L13
addisp,sp,16
jr ra
.L13:
lw a0,12(sp)
lw a4,12(sp)
mul a0,a0,a4
lw a4,12(sp)
addia4,a4,1
sw a4,12(sp)
j .L12
[Bug c/112559] New: The -fno-builtin option affects the instruction generation of the program
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112559 Bug ID: 112559 Summary: The -fno-builtin option affects the instruction generation of the program Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: c Assignee: unassigned at gcc dot gnu.org Reporter: mumuxi_ll at outlook dot com Target Milestone: --- Created attachment 56600 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56600=edit C source code Upon compiling a function, it was observed that adding the -fno-builtin option resulted in the compilation of line 2795, where the set_head_size function in the mEMALIGn function occurs. Without the -fno-builtin option, the set_head_size does not appear in the assembly code. Does the gcc behavior change when processing -fno-builtin?
[Bug target/112538] New: [RISC-V] Failed to disable V-ext autovectorization using the '--param riscv-autovec-preference=none'
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112538
Bug ID: 112538
Summary: [RISC-V] Failed to disable V-ext autovectorization
using the '--param riscv-autovec-preference=none'
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: mumuxi_ll at outlook dot com
Target Milestone: ---
Here is my test case:
```
#include
typedef charStr_30 [31];
Str_30 Str_2_Loc;
void foo(void)
{
strcpy(Str_2_Loc, "DHRYSTONE PROGRAM");
}
```
Compiled with riscv64-unknown-elf-gcc -march=rv32imafdc_zve32f -mabi=ilp32d -S
rvv_autovec_bug.c --param riscv-autovec-preference=none
The result is:
.string "DHRYSTONE PROGRAM"
.text
.align 1
.globl foo
.type foo, @function
foo:
addisp,sp,-16
sw ra,12(sp)
sw s0,8(sp)
addis0,sp,16
lui a5,%hi(Str_2_Loc)
addia3,a5,%lo(Str_2_Loc)
lui a5,%hi(.LC0)
addia4,a5,%lo(.LC0)
mv a5,a3
vsetivlizero,9,e16,m8,ta,ma
vle16.v v8,0(a4)
vsetivlizero,9,e16,m8,ta,ma
vse16.v v8,0(a5)
nop
lw ra,12(sp)
lw s0,8(sp)
addisp,sp,16
jr ra
It still generates the v-ext instructions automatically, which seems that the
"--param riscv-autovec-preference=none" did not work.
[Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621 --- Comment #2 from liu xu --- I'm sorry about that and will notice that next time. The toolchain I used was built using the gcc master branch, and another point that needs to be added is that only the vadd.vi instruction with mask will encounter the above problem, and without mask, it will not. Looking forward to your reply！
[Bug middle-end/111621] New: [RISC-V] Bad register allocation in vadd.vi may cause operational error
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621 Bug ID: 111621 Summary: [RISC-V] Bad register allocation in vadd.vi may cause operational error Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: mumuxi_ll at outlook dot com Target Milestone: --- Hi; My source code can be fond at https://godbolt.org/z/8v9Wxx9Yf. The porblem is that when compiling with -O2/-O3, vadd.vi will allocate a different register for vd compared to vs2, then the actual operation will only update the first data in vd instead of all. In cases such as -O0, vadd.vi will allocate the same registers to vd and vs2, and all vd values will be refreshed after execution. Thanks!
[Bug target/110448] New: [RISC-V] RVV intrinsic api test error
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110448 Bug ID: 110448 Summary: [RISC-V] RVV intrinsic api test error Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: mumuxi_ll at outlook dot com Target Milestone: --- Too few arguments error to function '__riscv_vsadd_vv_i16m8' when testing rvv intrinsic api according to https://github.com/riscv-non-isa/rvv-intrinsic-doc with gcc-trunk branch. Here is the tset link:https://godbolt.org/z/nYr6TKPbq. But it succeed with gcc-13.1: https://godbolt.org/z/oavWf96o1.
