[Bug testsuite/105620] [13 regression] g++.dg/tsan/pr88018.C fails after r13-456-geccbd7fcee5bbf
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105620 pc at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #4 from pc at gcc dot gnu.org --- Revert of the move of the file that caused this issue has been pushed to trunk. Marking as FIXED.
[Bug target/104257] rs6000/*intrin.h headers using non-uglified automatic variables
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104257 pc at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #6 from pc at gcc dot gnu.org --- Fixed on trunk (in gcc-12 window, including a subsequent fix for the fix by Jakub (Thanks!)), backported (without the issue requiring the subsequent fix) to gcc-11 and gcc-10. Closing.
[Bug testsuite/105620] [13 regression] g++.dg/tsan/pr88018.C fails after r13-456-geccbd7fcee5bbf
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105620 pc at gcc dot gnu.org changed: What|Removed |Added Last reconfirmed||2022-05-18 Ever confirmed|0 |1 Status|UNCONFIRMED |ASSIGNED
[Bug testsuite/105620] [13 regression] g++.dg/tsan/pr88018.C fails after r13-456-geccbd7fcee5bbf
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105620
pc at gcc dot gnu.org changed:
What|Removed |Added
CC||pc at gcc dot gnu.org
--- Comment #1 from pc at gcc dot gnu.org ---
gcc/testsuite/g++.dg/tsan/pr88018.C includes one of the files moved in the
patch:
```
// { dg-skip-if "" { *-*-* } { "*" } { "-O0" } }
// { dg-options "-fsanitize=thread -fno-ipa-pure-const -O1
-fno-inline-functions-called-once -w" }
#include "../pr69667.C"
```
I admit ignorance on the meaning or importance of the directory structure here.
Indeed the patch which moved pr69667.C was a small attempt to clean things up a
bit.
Would it be correct to move this test from g++.dg/tsan to g++.target/powerpc ?
(Or, do I need to move pr69667.C back to its original location? Or, do I need
to update the path within pr88018.C, which seems like the worst option?)
Did I miss this because I used `--disable-libsanitizer`, or because I just
missed that there was a FAIL for a test which I mistakenly thought was
unrelated to my changes? (There are a lot of FAILs to ignore.)
[Bug target/103605] [PowerPC] fmin/fmax should be inlined always with xsmindp/xsmaxdp
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103605 --- Comment #5 from pc at gcc dot gnu.org --- I modified the testcase from comment #3 to clear-before and check-after FE_INVALID exception bit for each operation: -- $ /opt/gcc-nightly/trunk/bin/gcc -O2 -o xsmindp-test xsmindp-test.c xsmindp.c -lm && ./xsmindp-test a b (src1, src2): fmin:I b-in:I asm:I (+3.0, +3.0): +3.0;0 +3.0;0 +3.0;0 (+3.0, NAN): +3.0;0 +nan;0 +3.0;0 ( NAN, +3.0): +3.0;0 +3.0;0 +3.0;0 ( NAN, NAN): +nan;0 +nan;0 +nan;0 (+3.0, SNAN): +nan;1 +nan;1 +nan;1 (SNAN, +3.0): +nan;1 +3.0;1 +nan;1 (SNAN, SNAN): +nan;1 +nan;1 +nan;1 $ /opt/gcc-nightly/trunk/bin/gcc -O2 -ffast-math -o xsmindp-test xsmindp-test.c xsmindp.c -lm && ./xsmindp-test a b (src1, src2): fmin:I b-in:I asm:I (+3.0, +3.0): +3.0;0 +3.0;0 +3.0;0 (+3.0, NAN): +nan;0 +nan;0 +3.0;0 ( NAN, +3.0): +3.0;0 +3.0;0 +3.0;0 ( NAN, NAN): +nan;0 +nan;0 +nan;0 (+3.0, SNAN): +nan;1 +nan;1 +nan;1 (SNAN, +3.0): +3.0;1 +3.0;1 +nan;1 (SNAN, SNAN): +nan;1 +nan;1 +nan;1 -- Without -ffast-math, fmin() matches xsmindp. With -ffast-math, fmin() matches xsmincdp.
[Bug target/103605] [PowerPC] fmin/fmax should be inlined always with xsmindp/xsmaxdp
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103605
--- Comment #3 from pc at gcc dot gnu.org ---
Here's a test which exercises all three options:
- fmin () (glibc 2.28)
- xsmincdp (ironically, via __builtin_vsx_xsmindp)
- xsmindp (via asm)
--
$ cat xsmindp.c
#include
#include
int main (int argc) {
double d0 = argc, d1 = argc+1;
double rf, rb, rx;
printf ("(src1, src2): fmin b-in asm\n");
rf = fmin (d0, d1);
rb = __builtin_vsx_xsmindp (d0, d1);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d0), "wa" (d1));
printf ("(+3.0, +3.0): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
d1 = NAN;
rf = fmin (d0, d1);
rb = __builtin_vsx_xsmindp (d0, d1);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d0), "wa" (d1));
printf ("(+3.0, NAN): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
rf = fmin (d1, d0);
rb = __builtin_vsx_xsmindp (d1, d0);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d1), "wa" (d0));
printf ("( NAN, +3.0): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
d0 = NAN;
rf = fmin (d0, d1);
rb = __builtin_vsx_xsmindp (d0, d1);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d0), "wa" (d1));
printf ("( NAN, NAN): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
d0 = argc, d1 = argc+1;
d1 = __builtin_nans ("0");
rf = fmin (d0, d1);
rb = __builtin_vsx_xsmindp (d0, d1);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d0), "wa" (d1));
printf ("(+3.0, SNAN): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
rf = fmin (d1, d0);
rb = __builtin_vsx_xsmindp (d1, d0);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d1), "wa" (d0));
printf ("(SNAN, +3.0): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
d0 = __builtin_nans ("0");
rf = fmin (d0, d1);
rb = __builtin_vsx_xsmindp (d0, d1);
asm ("xsmindp %0,%1,%2" : "=wa" (rx) : "wa" (d0), "wa" (d1));
printf ("(SNAN, SNAN): %+3.1f %+3.1f %+3.1f\n", rf, rb, rx);
return 0;
}
$ /opt/gcc-nightly/trunk/bin/gcc --version
gcc (GCC) 12.0.1 20220426 (experimental) [remotes/origin/HEAD
r12-8269-gcd4acb8cd9]
Copyright (C) 2022 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ /opt/gcc-nightly/trunk/bin/gcc -fsignaling-nans -D_WANT_SNAN -o xsmindp
xsmindp.c -O0 -lm && ./xsmindp
(src1, src2): fmin b-in asm
(+3.0, +3.0): +1.0 +1.0 +1.0
(+3.0, NAN): +1.0 +nan +1.0
( NAN, +3.0): +1.0 +1.0 +1.0
( NAN, NAN): +nan +nan +nan
(+3.0, SNAN): +nan +nan +nan
(SNAN, +3.0): +nan +1.0 +nan
(SNAN, SNAN): +nan +nan +nan
$ /opt/gcc-nightly/trunk/bin/gcc -fsignaling-nans -D_WANT_SNAN -o xsmindp
xsmindp.c -O3 -mcpu=power10 -lm && ./xsmindp
(src1, src2): fmin b-in asm
(+3.0, +3.0): +1.0 +1.0 +1.0
(+3.0, NAN): +1.0 +nan +1.0
( NAN, +3.0): +1.0 +nan +1.0
( NAN, NAN): +nan +nan +nan
(+3.0, SNAN): +nan +nan +nan
(SNAN, +3.0): +nan +1.0 +nan
(SNAN, SNAN): +nan +nan +nan
$ /opt/gcc-nightly/trunk/bin/gcc -fsignaling-nans -D_WANT_SNAN -o xsmindp
xsmindp.c -O3 -mcpu=power10 -lm -ffast-math && ./xsmindp
(src1, src2): fmin b-in asm
(+3.0, +3.0): +1.0 +1.0 +1.0
(+3.0, NAN): +nan +nan +1.0
( NAN, +3.0): +nan +nan +1.0
( NAN, NAN): +nan +nan +nan
(+3.0, SNAN): +nan +nan +nan
(SNAN, +3.0): +nan +nan +nan
(SNAN, SNAN): +nan +nan +nan
--
Without -ffast-math, the current semantics of fmin() match those of xsmindp.
With -ffast-math, the current semantics of fmin() match those of xsmincdp.
[Bug target/104901] gcc/config/rs6000/mm_malloc.h:46: incorrectLogicOperator
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104901 pc at gcc dot gnu.org changed: What|Removed |Added CC||pc at gcc dot gnu.org --- Comment #5 from pc at gcc dot gnu.org --- (In reply to Segher Boessenkool from comment #4) > is this micro-optimisation useful at all, don't > posix_memalign and malloc end up the same under the covers anyway? posix_memalign returns memory aligned to a specified power-of-2 alignment. malloc returns memory aligned to some ABI minimum. (You already know this, I'm sure.) The code will use malloc if it can, and posix_memalign otherwise. There may be a slight advantage to using malloc instead of posix_memalign. The paths are indeed different. I'm not sure why the floor is raised after determining not to call malloc: -- if (__alignment == __malloc_align && __alignment == __vec_align) return malloc (__size); if (__alignment < __vec_align) __alignment = __vec_align; -- (I probably would've written the code slightly differently.) It appears to me that the identified code would be always false on a 32-bit system, where __malloc_align would be computed as 64 bits, and _vec_align as 128 bits. It would be always true on a 64-bit system (128 == 128). All that being said, I'm not sure I see any problem with the code, and maybe the analyzer is being a bit overzealous? FWIW, the code was likely taken as an analog to gcc/config/i386/pmm_malloc.h: -- if (__alignment == 1) return malloc (__size); if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4)) __alignment = sizeof (void *); if (posix_memalign (&__ptr, __alignment, __size) == 0) return __ptr; --
[Bug testsuite/102719] [12 regression] several failures after r12-4337
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102719 pc at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED --- Comment #4 from pc at gcc dot gnu.org --- Fixed with noted commits.
[Bug target/104257] rs6000/*intrin.h headers using non-uglified automatic variables
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104257 pc at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |pc at gcc dot gnu.org Ever confirmed|0 |1 Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2022-02-17
[Bug ipa/102059] Incorrect always_inline diagnostic in LTO mode with #pragma GCC target("cpu=power10")
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102059 pc at gcc dot gnu.org changed: What|Removed |Added CC||pc at gcc dot gnu.org --- Comment #27 from pc at gcc dot gnu.org --- There was a commit related to this bug, but it is still in ASSIGNED state, so I'm not sure if this was to be considered "fixed", but... Chip discovered that, with a build of today's trunk, the original test case, and at least gcc.target/powerpc/pr102059-1.c still fail (I didn't try others), and it seems to be related to the presence of "-flto": -- $ gcc -c gcc/testsuite/gcc.target/powerpc/pr102059-1.c -O2 -mcpu=power8 -Wno-attributes -flto gcc/testsuite/gcc.target/powerpc/pr102059-1.c: In function 'bar': gcc/testsuite/gcc.target/powerpc/pr102059-1.c:8:1: error: inlining failed in call to 'always_inline' 'foo': target specific option mismatch 8 | foo (int *b) | ^~~ gcc/testsuite/gcc.target/powerpc/pr102059-1.c:18:8: note: called from here 18 | *a = foo (a); |^~~ $ gcc -c gcc/testsuite/gcc.target/powerpc/pr102059-1.c -O2 -mcpu=power8 -Wno-attributes $ -- The testcases included with the commit do not use "-flto", so these tests are PASSing.
[Bug target/103605] [PowerPC] fmin/fmax should be inlined always with xsmindp/xsmaxdp
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103605
--- Comment #1 from pc at gcc dot gnu.org ---
$ cat fmin.c
#include
double fm (double d0, double d1) {
return fmin (d0, d1);
}
[Bug target/103605] New: [PowerPC] fmin/fmax should be inlined always with xsmindp/xsmaxdp
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103605 Bug ID: 103605 Summary: [PowerPC] fmin/fmax should be inlined always with xsmindp/xsmaxdp Product: gcc Version: 11.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: pc at gcc dot gnu.org Target Milestone: --- -- $ gcc --version gcc (GCC) 11.2.1 20210728 (Red Hat 11.2.1-2) [...] $ gcc -c -O2 fmin.c && objdump -dr fmin.o 0: 00 00 4c 3c addis r2,r12,0 0: R_PPC64_REL16_HA .TOC. 4: 00 00 42 38 addir2,r2,0 4: R_PPC64_REL16_LO .TOC.+0x4 8: a6 02 08 7c mflrr0 c: 10 00 01 f8 std r0,16(r1) 10: e1 ff 21 f8 stdur1,-32(r1) 14: 01 00 00 48 bl 14 14: R_PPC64_REL24 fmin 18: 00 00 00 60 nop 1c: 20 00 21 38 addir1,r1,32 20: 10 00 01 e8 ld r0,16(r1) 24: a6 03 08 7c mtlrr0 28: 20 00 80 4e blr $ gcc -c -O2 fmin.c -ffast-math && objdump -dr fmin.o 0: 40 14 21 f0 xsmincdp vs1,vs1,vs2 4: 20 00 80 4e blr -- And it appears that a better instruction choice in the above case is xsmindp, and it can be used with and without "-ffast-math", as it matches the semantics required of fmin. Similarly, xsmaxdp with fmax.
[Bug testsuite/103545] [12 regression] gcc.target/powerpc/undef-bool-2.c fails after r12-5580
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103545 pc at gcc dot gnu.org changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |pc at gcc dot gnu.org Resolution|--- |FIXED Status|UNCONFIRMED |RESOLVED CC||pc at gcc dot gnu.org --- Comment #2 from pc at gcc dot gnu.org --- Fixed on trunk (commit above).
[Bug target/91534] New: some defined builtins are not usable
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91534
Bug ID: 91534
Summary: some defined builtins are not usable
Product: gcc
Version: 10.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pc at gcc dot gnu.org
Target Milestone: ---
On a ppc64le system, some builtins which appear to have the beginnings of
support are not usable at compilation time.
Example from gcc/config/rs6000/rs6000-builtin.def:
BU_VSX_X (XSMADDMDP, "xsmaddmdp", FP)
$ cat xsmaddmdp.c
#include
#include
double foo(double a, double b, double c) {
double d = __builtin_vsx_xsmaddmdp (2.0, 3.0, 11.0);
return d;
}
$ /opt/at12.0/bin/gcc --version
gcc (GCC) 8.2.1 20180813 (Advance-Toolchain-at12.0) [revision 263510]
$ /opt/at12.0/bin/gcc -c xsmaddmdp.c -mcpu=power9
xsmaddmdp.c: In function ‘foo’:
xsmaddmdp.c:4:13: warning: implicit declaration of function
‘__builtin_vsx_xsmaddmdp’; did you mean ‘__builtin_vsx_xvmadddp’?
[-Wimplicit-function-declaration]
Unscientifically, I took all of the __builtin_{altivec,vmx,vsx,vec} strings
from /opt/at12.0/libexec/gcc/powerpc64le-linux-gnu/8.2.1/cc1, and the following
builtins exhibit the same issue:
implicit declaration of function ‘__builtin_altivec_mask_for_store’
implicit declaration of function ‘__builtin_altivec_vec_init_v4si’
implicit declaration of function ‘__builtin_altivec_vec_init_v8hi’
implicit declaration of function ‘__builtin_altivec_vec_init_v16qi’
implicit declaration of function ‘__builtin_altivec_vec_init_v4sf’
implicit declaration of function ‘__builtin_altivec_vec_set_v4si’
implicit declaration of function ‘__builtin_altivec_vec_set_v8hi’
implicit declaration of function ‘__builtin_altivec_vec_set_v16qi’
implicit declaration of function ‘__builtin_altivec_vec_set_v4sf’
implicit declaration of function ‘__builtin_altivec_vec_ext_v4si’
implicit declaration of function ‘__builtin_altivec_vec_ext_v8hi’
implicit declaration of function ‘__builtin_altivec_vec_ext_v16qi’
implicit declaration of function ‘__builtin_altivec_vec_ext_v4sf’
implicit declaration of function ‘__builtin_vec_sldw’
implicit declaration of function ‘__builtin_vsx_lxsdx’
implicit declaration of function ‘__builtin_vsx_lxvdsx’
implicit declaration of function ‘__builtin_vsx_stxsdx’
implicit declaration of function ‘__builtin_vsx_xsabsdp’
implicit declaration of function ‘__builtin_vsx_xsadddp’
implicit declaration of function ‘__builtin_vsx_xscmpodp’
implicit declaration of function ‘__builtin_vsx_xscmpudp’
implicit declaration of function ‘__builtin_vsx_xscvdpsxds’
implicit declaration of function ‘__builtin_vsx_xscvdpsxws’
implicit declaration of function ‘__builtin_vsx_xscvdpuxds’
implicit declaration of function ‘__builtin_vsx_xscvdpuxws’
implicit declaration of function ‘__builtin_vsx_xscvsxddp’
implicit declaration of function ‘__builtin_vsx_xscvuxddp’
implicit declaration of function ‘__builtin_vsx_xsdivdp’
implicit declaration of function ‘__builtin_vsx_xsmaddadp’
implicit declaration of function ‘__builtin_vsx_xsmaddmdp’
implicit declaration of function ‘__builtin_vsx_xsmovdp’
implicit declaration of function ‘__builtin_vsx_xsmsubadp’
implicit declaration of function ‘__builtin_vsx_xsmsubmdp’
implicit declaration of function ‘__builtin_vsx_xsmuldp’
implicit declaration of function ‘__builtin_vsx_xsnabsdp’
implicit declaration of function ‘__builtin_vsx_xsnegdp’
implicit declaration of function ‘__builtin_vsx_xsnmaddadp’
implicit declaration of function ‘__builtin_vsx_xsnmaddmdp’
implicit declaration of function ‘__builtin_vsx_xsnmsubadp’
implicit declaration of function ‘__builtin_vsx_xsnmsubmdp’
implicit declaration of function ‘__builtin_vsx_xssubdp’
implicit declaration of function ‘__builtin_vsx_vec_init_v1ti’
implicit declaration of function ‘__builtin_vsx_vec_init_v2df’
implicit declaration of function ‘__builtin_vsx_vec_init_v2di’
implicit declaration of function ‘__builtin_vsx_vec_set_v1ti’
implicit declaration of function ‘__builtin_vsx_vec_set_v2df’
implicit declaration of function ‘__builtin_vsx_vec_set_v2di’
implicit declaration of function ‘__builtin_vsx_vec_ext_v1ti’
implicit declaration of function ‘__builtin_vsx_vec_ext_v2df’
implicit declaration of function ‘__builtin_vsx_vec_ext_v2di’
implicit declaration of function ‘__builtin_altivec_xst_len_r’
...that is certainly not a complete set, because it excludes all of the form
__builtin_.
[Bug target/89721] New: __builtin_mffs sometimes optimized away
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89721 Bug ID: 89721 Summary: __builtin_mffs sometimes optimized away Product: gcc Version: 9.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: pc at gcc dot gnu.org Target Milestone: --- Created attachment 45969 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45969=edit test case where 3rd call to __builtin_mffs() is optimized away I have a testcase that reports arguably incorrect results under any optimization, correct results without optimization. This is with GCC 7.3, 8.2, and trunk. Testcase attached. Without optimization: -- $ ./mffs-bug fpscr = 0x0002 fpscr = 0x0003 fpscr = 0x0001 -- With -O: -- $ ./mffs-bug-O fpscr = 0x0002 fpscr = 0x0003 fpscr = 0x0003 If I remove interesting pieces of the code above the last stanza, the problem disappears. The generated assembly is missing the final (of 3) "mffs" instructions. Below, the instruction is expected roughly between 76c and 770: -- ... 1718: li r3,2 171c: bl 1560 <0018.plt_call.fesetround@@GLIBC_2.17> 1720: ld r2,24(r1) 1724: mffsf0 1728: addis r31,r2,-2 172c: addir31,r31,-30144 1730: mfvsrd r4,vs0 1734: mr r3,r31 1738: bl 1540 <0018.plt_call.printf@@GLIBC_2.17> 173c: ld r2,24(r1) 1740: li r3,3 1744: bl 1560 <0018.plt_call.fesetround@@GLIBC_2.17> 1748: ld r2,24(r1) 174c: mffsf0 1750: fmr f31,f0 1754: mfvsrd r4,vs0 1758: mr r3,r31 175c: bl 1540 <0018.plt_call.printf@@GLIBC_2.17> 1760: ld r2,24(r1) 1764: li r3,1 1768: bl 1560 <0018.plt_call.fesetround@@GLIBC_2.17> 176c: ld r2,24(r1) 1770: mfvsrd r4,vs31 1774: mr r3,r31 1778: bl 1540 <0018.plt_call.printf@@GLIBC_2.17> --
[Bug target/89339] sse-movmskb-1.c fails for PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89339 pc at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #3 from pc at gcc dot gnu.org --- fixes committed
[Bug target/89338] sse-cvtss2si-[12].c fails on PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89338 pc at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #3 from pc at gcc dot gnu.org --- fixes committed
[Bug target/89338] sse-cvtss2si-[12].c fails on PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89338 --- Comment #2 from pc at gcc dot gnu.org --- Author: pc Date: Mon Feb 25 19:36:05 2019 New Revision: 269195 URL: https://gcc.gnu.org/viewcvs?rev=269195=gcc=rev Log: [rs6000] PR89338, PR89339: Fix compat vector intrinsics for BE and 32-bit Test FAILS: sse2-cvtpd2dq-1, sse2-cvtpd2ps, sse2-cvttpd2dq on powerpc64 (big-endian). _mm_cvtpd_epi32, _mm_cvtpd_ps, _mm_cvttpd_epi32: Type conversion from vector doubleword type to vector word type leaves the results in even lanes in big endian mode. Test FAILS: sse-cvtss2si-1, sse-cvtss2si-2, sse-movmskb-1 on powerpc (32-bit big-endian). Incorrect type for interpreting the result from mfvsrd instruction leads to incorrect results. Also, mfvsrd instruction only works as expected in 64-bit mode or for 32-bit quantities in 32-bit mode. A more general, if slower, solution is needed for 32-bit mode. 2019-02-25 Paul A. Clarke [gcc] * config/rs6000/emmintrin.h (_mm_cvtpd_epi32): Fix big endian. (_mm_cvtpd_ps): Likewise. (_mm_cvttpd_epi32): Likewise. PR target/89338 * config/rs6000/xmmintrin.h (_mm_cvtss_f32): Fix type mismatch. (_mm_cvt_ss2si): Fix type mismatch and 32-bit. PR target/89339 * config/rs6000/xmmintrin.h (_mm_movemask_pi8): Fix 32-bit. Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/emmintrin.h trunk/gcc/config/rs6000/xmmintrin.h
[Bug target/89339] sse-movmskb-1.c fails for PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89339 --- Comment #2 from pc at gcc dot gnu.org --- Author: pc Date: Mon Feb 25 19:36:05 2019 New Revision: 269195 URL: https://gcc.gnu.org/viewcvs?rev=269195=gcc=rev Log: [rs6000] PR89338, PR89339: Fix compat vector intrinsics for BE and 32-bit Test FAILS: sse2-cvtpd2dq-1, sse2-cvtpd2ps, sse2-cvttpd2dq on powerpc64 (big-endian). _mm_cvtpd_epi32, _mm_cvtpd_ps, _mm_cvttpd_epi32: Type conversion from vector doubleword type to vector word type leaves the results in even lanes in big endian mode. Test FAILS: sse-cvtss2si-1, sse-cvtss2si-2, sse-movmskb-1 on powerpc (32-bit big-endian). Incorrect type for interpreting the result from mfvsrd instruction leads to incorrect results. Also, mfvsrd instruction only works as expected in 64-bit mode or for 32-bit quantities in 32-bit mode. A more general, if slower, solution is needed for 32-bit mode. 2019-02-25 Paul A. Clarke [gcc] * config/rs6000/emmintrin.h (_mm_cvtpd_epi32): Fix big endian. (_mm_cvtpd_ps): Likewise. (_mm_cvttpd_epi32): Likewise. PR target/89338 * config/rs6000/xmmintrin.h (_mm_cvtss_f32): Fix type mismatch. (_mm_cvt_ss2si): Fix type mismatch and 32-bit. PR target/89339 * config/rs6000/xmmintrin.h (_mm_movemask_pi8): Fix 32-bit. Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/emmintrin.h trunk/gcc/config/rs6000/xmmintrin.h
[Bug target/89338] sse-cvtss2si-[12].c fails on PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89338 pc at gcc dot gnu.org changed: What|Removed |Added Target Milestone|--- |9.0 --- Comment #1 from pc at gcc dot gnu.org --- Fix posted for review: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg01589.html
[Bug target/89339] sse-movmskb-1.c fails for PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89339 pc at gcc dot gnu.org changed: What|Removed |Added Target Milestone|--- |9.0 --- Comment #1 from pc at gcc dot gnu.org --- Fix posted for review: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg01589.html
[Bug tree-optimization/53991] _mm_popcnt_u64 fails with -O3 -fgnu-tm
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53991 pc at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|NEW --- Comment #13 from pc at gcc dot gnu.org --- sorry, changed the state of this bug instead of another. resetting to "NEW".
[Bug target/89339] sse-movmskb-1.c fails for PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89339 pc at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2019-02-19 Ever confirmed|0 |1
[Bug target/89338] sse-cvtss2si-[12].c fails on PPC Big Endian
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89338 pc at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2019-02-19 CC||pc at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |pc at gcc dot gnu.org Ever confirmed|0 |1
[Bug tree-optimization/53991] _mm_popcnt_u64 fails with -O3 -fgnu-tm
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53991 pc at gcc dot gnu.org changed: What|Removed |Added Status|NEW |ASSIGNED CC||pc at gcc dot gnu.org
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 pc at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED --- Comment #7 from pc at gcc dot gnu.org --- Fixed in trunk, ibm/gcc-8-branch, ibm/gcc-7-branch.
[Bug target/88408] [9 regression] r266868 breaks gcc.target/powerpc/undef-bool-2.c on powerpc64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88408 --- Comment #5 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 20 18:22:24 2018 New Revision: 267309 URL: https://gcc.gnu.org/viewcvs?rev=267309=gcc=rev Log: 2018-12-20 Paul Clarke [gcc] Backport from trunk 267261 2018-12-19 Paul A. Clarke * config/rs6000/tmmintrin.h (_mm_hadds_epi16): Vector lanes swapped. (_mm_hsub_epi32): Likewise. (_mm_shuffle_epi8): Fix reversed interpretation of parameters. (_mm_shuffle_pi8): Likewise. (_mm_addubs_pi16): Likewise. 266895 2018-12-07 Paul A. Clarke PR target/88408 * config/rs6000/mmintrin.h (_mm_packs_pu16): Correctly use "__vector". 266869 2018-12-06 Paul A. Clarke PR target/88316 * config/rs6000/smmintrin.h: New file. * config.gcc: Add smmintrin.h to extra_headers for powerpc*-*-*. 266868 2018-12-03 Paul A. Clarke PR target/88316 * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. (_mm_unpacklo_pi8): Likewise. (_mm_mulhi_pi16): Likewise. (_mm_packs_pi16): Fix for big-endian. Use preferred API. (_mm_packs_pi32): Likewise. (_mm_packs_pu16): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. (_mm_cvtss_si64): Likewise. (_mm_cvtpi32x2_ps): Likewise. (_mm_shuffle_ps): Likewise. (_mm_movemask_pi8): Likewise. (_mm_mulhi_pu16): Likewise. (_mm_sad_pu8): Likewise. (_mm_sad_pu8): Likewise. (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. (_mm_cvtpu8_ps): Likewise. (_mm_movemask_ps): Better #else case for big-endian (no functional change). (_mm_shuffle_pi16): Likewise. * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. Better #else case for big-endian (no functional change). (_mm_movemask_epi8): Likewise. (_mm_shufflehi_epi16): Likewise. (_mm_shufflelo_epi16): Likewise. (_mm_shuffle_epi32): Likewise. (_mm_mul_epu32): Fix for big-endian. (_mm_bsrli_si128): Likewise. (_mm_cvtps_pd): Better #else case for big endian. (_mm_mulhi_epi16): Likewise. (_mm_mul_epu32): Likewise. (_mm_slli_si128): Likewise. (_mm_sll_epi16): Likewise. (_mm_sll_epi32): Likewise. (_mm_sra_epi16): Likewise. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_mulhi_epu16): Likewise. (_mm_sad_epu8): Likewise. * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. (_mm_sub_ps): Likewise. * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. * gcc/config/rs6000/tmmintrin.h (_mm_alignr_epi8): Use ENDIAN macros consistently (no functional changes). (_mm_alignr_pi8): Likewise. 265601 2018-10-29 Paul A. Clarke * gcc/config/rs6000/mmintrin.h (_mm_packs_pi16, _mm_packs_pi32, _mm_packs_pu16, _mm_unpackhi_pi8, _mm_unpacklo_pi8, _mm_add_pi8, _mm_add_pi16, _mm_add_pi32, _mm_sub_pi8, _mm_sub_pi16, _mm_sub_pi32, _mm_cmpgt_pi8, _mm_cmpeq_pi16, _mm_cmpgt_pi16, _mm_cmpeq_pi32, _mm_cmpgt_pi32, _mm_adds_pi8, _mm_adds_pi16, _mm_adds_pu8, _mm_adds_pu16, _mm_subs_pi8, _mm_subs_pi16, _mm_subs_pu8, _mm_subs_pu16, _mm_madd_pi16, _mm_mulhi_pi16, _mm_mullo_pi16, _mm_sll_pi16, _mm_sra_pi16, _mm_srl_pi16, _mm_set1_pi16, _mm_set1_pi8): Change 'vector' to '__vector'. * gcc/config/rs6000/xmmintrin.h (_mm_cvtps_pi32, _mm_cvttps_pi32, _mm_cvtps_pi16, _mm_cvtps_pi8, _mm_max_pi16, _mm_max_pu8, _mm_min_pi16, _mm_min_pu8, _mm_mulhi_pu16, _mm_shuffle_pi16, _mm_avg_pu8, _mm_avg_pu16): Likewise. And, whitespace corrections. 265542 2018-10-26 Paul A. Clarke * config/rs6000/tmmintrin.h: New file. * config.gcc (powerpc*-*-*): Add tmmintrin.h to extra_headers. 265535 2018-10-25 Paul A. Clarke * config/rs6000/mmintrin.h: Enable 32bit compilation. * config/rs6000/xmmintrin.h: Likewise. 265531 2018-10-26 Paul A. Clarke * config/rs6000/xmmintrin.h (_mm_extract_pi16): Fix for big-endian. 258988 2018-03-31 Segher Boessenkool PR target/83315 * config/rs6000/xmmintrin.h (_mm_set_ps, _mm_max_ps): Handle (quiet) NaN inputs correctly. [gcc/testsuite] Backport from trunk. 267271 2018-12-19 Paul A. Clarke * gcc.target/powerpc/ssse3-check.h: Enable tests to run. * gcc.target/powerpc/ssse3-pabsb.c: Code fixes for strict aliasing issues. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/pow
[Bug target/83315] PowerPC xmmintrin.h emulation for _mm_{min,max}_ps not semantically equivalent
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83315 --- Comment #4 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 20 18:22:24 2018 New Revision: 267309 URL: https://gcc.gnu.org/viewcvs?rev=267309=gcc=rev Log: 2018-12-20 Paul Clarke [gcc] Backport from trunk 267261 2018-12-19 Paul A. Clarke * config/rs6000/tmmintrin.h (_mm_hadds_epi16): Vector lanes swapped. (_mm_hsub_epi32): Likewise. (_mm_shuffle_epi8): Fix reversed interpretation of parameters. (_mm_shuffle_pi8): Likewise. (_mm_addubs_pi16): Likewise. 266895 2018-12-07 Paul A. Clarke PR target/88408 * config/rs6000/mmintrin.h (_mm_packs_pu16): Correctly use "__vector". 266869 2018-12-06 Paul A. Clarke PR target/88316 * config/rs6000/smmintrin.h: New file. * config.gcc: Add smmintrin.h to extra_headers for powerpc*-*-*. 266868 2018-12-03 Paul A. Clarke PR target/88316 * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. (_mm_unpacklo_pi8): Likewise. (_mm_mulhi_pi16): Likewise. (_mm_packs_pi16): Fix for big-endian. Use preferred API. (_mm_packs_pi32): Likewise. (_mm_packs_pu16): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. (_mm_cvtss_si64): Likewise. (_mm_cvtpi32x2_ps): Likewise. (_mm_shuffle_ps): Likewise. (_mm_movemask_pi8): Likewise. (_mm_mulhi_pu16): Likewise. (_mm_sad_pu8): Likewise. (_mm_sad_pu8): Likewise. (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. (_mm_cvtpu8_ps): Likewise. (_mm_movemask_ps): Better #else case for big-endian (no functional change). (_mm_shuffle_pi16): Likewise. * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. Better #else case for big-endian (no functional change). (_mm_movemask_epi8): Likewise. (_mm_shufflehi_epi16): Likewise. (_mm_shufflelo_epi16): Likewise. (_mm_shuffle_epi32): Likewise. (_mm_mul_epu32): Fix for big-endian. (_mm_bsrli_si128): Likewise. (_mm_cvtps_pd): Better #else case for big endian. (_mm_mulhi_epi16): Likewise. (_mm_mul_epu32): Likewise. (_mm_slli_si128): Likewise. (_mm_sll_epi16): Likewise. (_mm_sll_epi32): Likewise. (_mm_sra_epi16): Likewise. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_mulhi_epu16): Likewise. (_mm_sad_epu8): Likewise. * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. (_mm_sub_ps): Likewise. * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. * gcc/config/rs6000/tmmintrin.h (_mm_alignr_epi8): Use ENDIAN macros consistently (no functional changes). (_mm_alignr_pi8): Likewise. 265601 2018-10-29 Paul A. Clarke * gcc/config/rs6000/mmintrin.h (_mm_packs_pi16, _mm_packs_pi32, _mm_packs_pu16, _mm_unpackhi_pi8, _mm_unpacklo_pi8, _mm_add_pi8, _mm_add_pi16, _mm_add_pi32, _mm_sub_pi8, _mm_sub_pi16, _mm_sub_pi32, _mm_cmpgt_pi8, _mm_cmpeq_pi16, _mm_cmpgt_pi16, _mm_cmpeq_pi32, _mm_cmpgt_pi32, _mm_adds_pi8, _mm_adds_pi16, _mm_adds_pu8, _mm_adds_pu16, _mm_subs_pi8, _mm_subs_pi16, _mm_subs_pu8, _mm_subs_pu16, _mm_madd_pi16, _mm_mulhi_pi16, _mm_mullo_pi16, _mm_sll_pi16, _mm_sra_pi16, _mm_srl_pi16, _mm_set1_pi16, _mm_set1_pi8): Change 'vector' to '__vector'. * gcc/config/rs6000/xmmintrin.h (_mm_cvtps_pi32, _mm_cvttps_pi32, _mm_cvtps_pi16, _mm_cvtps_pi8, _mm_max_pi16, _mm_max_pu8, _mm_min_pi16, _mm_min_pu8, _mm_mulhi_pu16, _mm_shuffle_pi16, _mm_avg_pu8, _mm_avg_pu16): Likewise. And, whitespace corrections. 265542 2018-10-26 Paul A. Clarke * config/rs6000/tmmintrin.h: New file. * config.gcc (powerpc*-*-*): Add tmmintrin.h to extra_headers. 265535 2018-10-25 Paul A. Clarke * config/rs6000/mmintrin.h: Enable 32bit compilation. * config/rs6000/xmmintrin.h: Likewise. 265531 2018-10-26 Paul A. Clarke * config/rs6000/xmmintrin.h (_mm_extract_pi16): Fix for big-endian. 258988 2018-03-31 Segher Boessenkool PR target/83315 * config/rs6000/xmmintrin.h (_mm_set_ps, _mm_max_ps): Handle (quiet) NaN inputs correctly. [gcc/testsuite] Backport from trunk. 267271 2018-12-19 Paul A. Clarke * gcc.target/powerpc/ssse3-check.h: Enable tests to run. * gcc.target/powerpc/ssse3-pabsb.c: Code fixes for strict aliasing issues. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/pow
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 --- Comment #6 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 20 18:22:24 2018 New Revision: 267309 URL: https://gcc.gnu.org/viewcvs?rev=267309=gcc=rev Log: 2018-12-20 Paul Clarke [gcc] Backport from trunk 267261 2018-12-19 Paul A. Clarke * config/rs6000/tmmintrin.h (_mm_hadds_epi16): Vector lanes swapped. (_mm_hsub_epi32): Likewise. (_mm_shuffle_epi8): Fix reversed interpretation of parameters. (_mm_shuffle_pi8): Likewise. (_mm_addubs_pi16): Likewise. 266895 2018-12-07 Paul A. Clarke PR target/88408 * config/rs6000/mmintrin.h (_mm_packs_pu16): Correctly use "__vector". 266869 2018-12-06 Paul A. Clarke PR target/88316 * config/rs6000/smmintrin.h: New file. * config.gcc: Add smmintrin.h to extra_headers for powerpc*-*-*. 266868 2018-12-03 Paul A. Clarke PR target/88316 * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. (_mm_unpacklo_pi8): Likewise. (_mm_mulhi_pi16): Likewise. (_mm_packs_pi16): Fix for big-endian. Use preferred API. (_mm_packs_pi32): Likewise. (_mm_packs_pu16): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. (_mm_cvtss_si64): Likewise. (_mm_cvtpi32x2_ps): Likewise. (_mm_shuffle_ps): Likewise. (_mm_movemask_pi8): Likewise. (_mm_mulhi_pu16): Likewise. (_mm_sad_pu8): Likewise. (_mm_sad_pu8): Likewise. (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. (_mm_cvtpu8_ps): Likewise. (_mm_movemask_ps): Better #else case for big-endian (no functional change). (_mm_shuffle_pi16): Likewise. * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. Better #else case for big-endian (no functional change). (_mm_movemask_epi8): Likewise. (_mm_shufflehi_epi16): Likewise. (_mm_shufflelo_epi16): Likewise. (_mm_shuffle_epi32): Likewise. (_mm_mul_epu32): Fix for big-endian. (_mm_bsrli_si128): Likewise. (_mm_cvtps_pd): Better #else case for big endian. (_mm_mulhi_epi16): Likewise. (_mm_mul_epu32): Likewise. (_mm_slli_si128): Likewise. (_mm_sll_epi16): Likewise. (_mm_sll_epi32): Likewise. (_mm_sra_epi16): Likewise. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_mulhi_epu16): Likewise. (_mm_sad_epu8): Likewise. * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. (_mm_sub_ps): Likewise. * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. * gcc/config/rs6000/tmmintrin.h (_mm_alignr_epi8): Use ENDIAN macros consistently (no functional changes). (_mm_alignr_pi8): Likewise. 265601 2018-10-29 Paul A. Clarke * gcc/config/rs6000/mmintrin.h (_mm_packs_pi16, _mm_packs_pi32, _mm_packs_pu16, _mm_unpackhi_pi8, _mm_unpacklo_pi8, _mm_add_pi8, _mm_add_pi16, _mm_add_pi32, _mm_sub_pi8, _mm_sub_pi16, _mm_sub_pi32, _mm_cmpgt_pi8, _mm_cmpeq_pi16, _mm_cmpgt_pi16, _mm_cmpeq_pi32, _mm_cmpgt_pi32, _mm_adds_pi8, _mm_adds_pi16, _mm_adds_pu8, _mm_adds_pu16, _mm_subs_pi8, _mm_subs_pi16, _mm_subs_pu8, _mm_subs_pu16, _mm_madd_pi16, _mm_mulhi_pi16, _mm_mullo_pi16, _mm_sll_pi16, _mm_sra_pi16, _mm_srl_pi16, _mm_set1_pi16, _mm_set1_pi8): Change 'vector' to '__vector'. * gcc/config/rs6000/xmmintrin.h (_mm_cvtps_pi32, _mm_cvttps_pi32, _mm_cvtps_pi16, _mm_cvtps_pi8, _mm_max_pi16, _mm_max_pu8, _mm_min_pi16, _mm_min_pu8, _mm_mulhi_pu16, _mm_shuffle_pi16, _mm_avg_pu8, _mm_avg_pu16): Likewise. And, whitespace corrections. 265542 2018-10-26 Paul A. Clarke * config/rs6000/tmmintrin.h: New file. * config.gcc (powerpc*-*-*): Add tmmintrin.h to extra_headers. 265535 2018-10-25 Paul A. Clarke * config/rs6000/mmintrin.h: Enable 32bit compilation. * config/rs6000/xmmintrin.h: Likewise. 265531 2018-10-26 Paul A. Clarke * config/rs6000/xmmintrin.h (_mm_extract_pi16): Fix for big-endian. 258988 2018-03-31 Segher Boessenkool PR target/83315 * config/rs6000/xmmintrin.h (_mm_set_ps, _mm_max_ps): Handle (quiet) NaN inputs correctly. [gcc/testsuite] Backport from trunk. 267271 2018-12-19 Paul A. Clarke * gcc.target/powerpc/ssse3-check.h: Enable tests to run. * gcc.target/powerpc/ssse3-pabsb.c: Code fixes for strict aliasing issues. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/pow
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 --- Comment #5 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 20 15:25:15 2018 New Revision: 267301 URL: https://gcc.gnu.org/viewcvs?rev=267301=gcc=rev Log: 2018-12-20 Paul Clarke [gcc] Backport from trunk 267261 2018-12-19 Paul A. Clarke * config/rs6000/tmmintrin.h (_mm_hadds_epi16): Vector lanes swapped. (_mm_hsub_epi32): Likewise. (_mm_shuffle_epi8): Fix reversed interpretation of parameters. (_mm_shuffle_pi8): Likewise. (_mm_addubs_pi16): Likewise. 266895 2018-12-07 Paul A. Clarke PR target/88408 * config/rs6000/mmintrin.h (_mm_packs_pu16): Correctly use "__vector". 266869 2018-12-06 Paul A. Clarke PR target/88316 * config/rs6000/smmintrin.h: New file. * config.gcc: Add smmintrin.h to extra_headers for powerpc*-*-*. 266868 2018-12-03 Paul A. Clarke PR target/88316 * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. (_mm_unpacklo_pi8): Likewise. (_mm_mulhi_pi16): Likewise. (_mm_packs_pi16): Fix for big-endian. Use preferred API. (_mm_packs_pi32): Likewise. (_mm_packs_pu16): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. (_mm_cvtss_si64): Likewise. (_mm_cvtpi32x2_ps): Likewise. (_mm_shuffle_ps): Likewise. (_mm_movemask_pi8): Likewise. (_mm_mulhi_pu16): Likewise. (_mm_sad_pu8): Likewise. (_mm_sad_pu8): Likewise. (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. (_mm_cvtpu8_ps): Likewise. (_mm_movemask_ps): Better #else case for big-endian (no functional change). (_mm_shuffle_pi16): Likewise. * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. Better #else case for big-endian (no functional change). (_mm_movemask_epi8): Likewise. (_mm_shufflehi_epi16): Likewise. (_mm_shufflelo_epi16): Likewise. (_mm_shuffle_epi32): Likewise. (_mm_mul_epu32): Fix for big-endian. (_mm_bsrli_si128): Likewise. (_mm_cvtps_pd): Better #else case for big endian. (_mm_mulhi_epi16): Likewise. (_mm_mul_epu32): Likewise. (_mm_slli_si128): Likewise. (_mm_sll_epi16): Likewise. (_mm_sll_epi32): Likewise. (_mm_sra_epi16): Likewise. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_mulhi_epu16): Likewise. (_mm_sad_epu8): Likewise. * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. (_mm_sub_ps): Likewise. * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. * gcc/config/rs6000/tmmintrin.h (_mm_alignr_epi8): Use ENDIAN macros consistently (no functional changes). (_mm_alignr_pi8): Likewise. 265601 2018-10-29 Paul A. Clarke * gcc/config/rs6000/mmintrin.h (_mm_packs_pi16, _mm_packs_pi32, _mm_packs_pu16, _mm_unpackhi_pi8, _mm_unpacklo_pi8, _mm_add_pi8, _mm_add_pi16, _mm_add_pi32, _mm_sub_pi8, _mm_sub_pi16, _mm_sub_pi32, _mm_cmpgt_pi8, _mm_cmpeq_pi16, _mm_cmpgt_pi16, _mm_cmpeq_pi32, _mm_cmpgt_pi32, _mm_adds_pi8, _mm_adds_pi16, _mm_adds_pu8, _mm_adds_pu16, _mm_subs_pi8, _mm_subs_pi16, _mm_subs_pu8, _mm_subs_pu16, _mm_madd_pi16, _mm_mulhi_pi16, _mm_mullo_pi16, _mm_sll_pi16, _mm_sra_pi16, _mm_srl_pi16, _mm_set1_pi16, _mm_set1_pi8): Change 'vector' to '__vector'. * gcc/config/rs6000/xmmintrin.h (_mm_cvtps_pi32, _mm_cvttps_pi32, _mm_cvtps_pi16, _mm_cvtps_pi8, _mm_max_pi16, _mm_max_pu8, _mm_min_pi16, _mm_min_pu8, _mm_mulhi_pu16, _mm_shuffle_pi16, _mm_avg_pu8, _mm_avg_pu16): Likewise. And, whitespace corrections. 265542 2018-10-26 Paul A. Clarke * config/rs6000/tmmintrin.h: New file. * config.gcc (powerpc*-*-*): Add tmmintrin.h to extra_headers. 265535 2018-10-25 Paul A. Clarke * config/rs6000/mmintrin.h: Enable 32bit compilation. * config/rs6000/xmmintrin.h: Likewise. 265531 2018-10-26 Paul A. Clarke * config/rs6000/xmmintrin.h (_mm_extract_pi16): Fix for big-endian. [gcc/testsuite] Backport from trunk. 267271 2018-12-19 Paul A. Clarke * gcc.target/powerpc/ssse3-check.h: Enable tests to run. * gcc.target/powerpc/ssse3-pabsb.c: Code fixes for strict aliasing issues. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/powerpc/ssse3-palignr.c: Likewise. * gcc.target/powerpc/ssse3-phaddd.c: Likewise. * gcc.target/powerpc/ssse3-phaddsw.c: Likewise. * gcc.target/powerpc/ssse3-phaddw.c
[Bug target/88408] [9 regression] r266868 breaks gcc.target/powerpc/undef-bool-2.c on powerpc64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88408 --- Comment #4 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 20 15:25:15 2018 New Revision: 267301 URL: https://gcc.gnu.org/viewcvs?rev=267301=gcc=rev Log: 2018-12-20 Paul Clarke [gcc] Backport from trunk 267261 2018-12-19 Paul A. Clarke * config/rs6000/tmmintrin.h (_mm_hadds_epi16): Vector lanes swapped. (_mm_hsub_epi32): Likewise. (_mm_shuffle_epi8): Fix reversed interpretation of parameters. (_mm_shuffle_pi8): Likewise. (_mm_addubs_pi16): Likewise. 266895 2018-12-07 Paul A. Clarke PR target/88408 * config/rs6000/mmintrin.h (_mm_packs_pu16): Correctly use "__vector". 266869 2018-12-06 Paul A. Clarke PR target/88316 * config/rs6000/smmintrin.h: New file. * config.gcc: Add smmintrin.h to extra_headers for powerpc*-*-*. 266868 2018-12-03 Paul A. Clarke PR target/88316 * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. (_mm_unpacklo_pi8): Likewise. (_mm_mulhi_pi16): Likewise. (_mm_packs_pi16): Fix for big-endian. Use preferred API. (_mm_packs_pi32): Likewise. (_mm_packs_pu16): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. (_mm_cvtss_si64): Likewise. (_mm_cvtpi32x2_ps): Likewise. (_mm_shuffle_ps): Likewise. (_mm_movemask_pi8): Likewise. (_mm_mulhi_pu16): Likewise. (_mm_sad_pu8): Likewise. (_mm_sad_pu8): Likewise. (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. (_mm_cvtpu8_ps): Likewise. (_mm_movemask_ps): Better #else case for big-endian (no functional change). (_mm_shuffle_pi16): Likewise. * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. Better #else case for big-endian (no functional change). (_mm_movemask_epi8): Likewise. (_mm_shufflehi_epi16): Likewise. (_mm_shufflelo_epi16): Likewise. (_mm_shuffle_epi32): Likewise. (_mm_mul_epu32): Fix for big-endian. (_mm_bsrli_si128): Likewise. (_mm_cvtps_pd): Better #else case for big endian. (_mm_mulhi_epi16): Likewise. (_mm_mul_epu32): Likewise. (_mm_slli_si128): Likewise. (_mm_sll_epi16): Likewise. (_mm_sll_epi32): Likewise. (_mm_sra_epi16): Likewise. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_mulhi_epu16): Likewise. (_mm_sad_epu8): Likewise. * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. (_mm_sub_ps): Likewise. * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. * gcc/config/rs6000/tmmintrin.h (_mm_alignr_epi8): Use ENDIAN macros consistently (no functional changes). (_mm_alignr_pi8): Likewise. 265601 2018-10-29 Paul A. Clarke * gcc/config/rs6000/mmintrin.h (_mm_packs_pi16, _mm_packs_pi32, _mm_packs_pu16, _mm_unpackhi_pi8, _mm_unpacklo_pi8, _mm_add_pi8, _mm_add_pi16, _mm_add_pi32, _mm_sub_pi8, _mm_sub_pi16, _mm_sub_pi32, _mm_cmpgt_pi8, _mm_cmpeq_pi16, _mm_cmpgt_pi16, _mm_cmpeq_pi32, _mm_cmpgt_pi32, _mm_adds_pi8, _mm_adds_pi16, _mm_adds_pu8, _mm_adds_pu16, _mm_subs_pi8, _mm_subs_pi16, _mm_subs_pu8, _mm_subs_pu16, _mm_madd_pi16, _mm_mulhi_pi16, _mm_mullo_pi16, _mm_sll_pi16, _mm_sra_pi16, _mm_srl_pi16, _mm_set1_pi16, _mm_set1_pi8): Change 'vector' to '__vector'. * gcc/config/rs6000/xmmintrin.h (_mm_cvtps_pi32, _mm_cvttps_pi32, _mm_cvtps_pi16, _mm_cvtps_pi8, _mm_max_pi16, _mm_max_pu8, _mm_min_pi16, _mm_min_pu8, _mm_mulhi_pu16, _mm_shuffle_pi16, _mm_avg_pu8, _mm_avg_pu16): Likewise. And, whitespace corrections. 265542 2018-10-26 Paul A. Clarke * config/rs6000/tmmintrin.h: New file. * config.gcc (powerpc*-*-*): Add tmmintrin.h to extra_headers. 265535 2018-10-25 Paul A. Clarke * config/rs6000/mmintrin.h: Enable 32bit compilation. * config/rs6000/xmmintrin.h: Likewise. 265531 2018-10-26 Paul A. Clarke * config/rs6000/xmmintrin.h (_mm_extract_pi16): Fix for big-endian. [gcc/testsuite] Backport from trunk. 267271 2018-12-19 Paul A. Clarke * gcc.target/powerpc/ssse3-check.h: Enable tests to run. * gcc.target/powerpc/ssse3-pabsb.c: Code fixes for strict aliasing issues. * gcc.target/powerpc/ssse3-pabsd.c: Likewise. * gcc.target/powerpc/ssse3-palignr.c: Likewise. * gcc.target/powerpc/ssse3-phaddd.c: Likewise. * gcc.target/powerpc/ssse3-phaddsw.c: Likewise. * gcc.target/powerpc/ssse3-phaddw.c
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 --- Comment #4 from pc at gcc dot gnu.org --- SSSE3 is still broken. Working on it...
[Bug target/88408] [9 regression] r266868 breaks gcc.target/powerpc/undef-bool-2.c on powerpc64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88408 pc at gcc dot gnu.org changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #3 from pc at gcc dot gnu.org --- Fix checked in, per comment #2
[Bug target/88408] [9 regression] r266868 breaks gcc.target/powerpc/undef-bool-2.c on powerpc64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88408 pc at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2018-12-07 CC||pc at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |pc at gcc dot gnu.org Ever confirmed|0 |1
[Bug target/88408] [9 regression] r266868 breaks gcc.target/powerpc/undef-bool-2.c on powerpc64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88408 --- Comment #2 from pc at gcc dot gnu.org --- Author: pc Date: Fri Dec 7 16:32:34 2018 New Revision: 266895 URL: https://gcc.gnu.org/viewcvs?rev=266895=gcc=rev Log: [rs6000] mmintrin.h: fix use of "vector" A recent patch inadvertently added the use of "vector" to mmintrin.h when all such uses should be "__vector". [gcc] 2018-12-07 Paul A. Clarke PR target/88408 * config/rs6000/mmintrin.h (_mm_packs_pu16): Correctly use "__vector". Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/mmintrin.h
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 --- Comment #3 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 6 22:14:55 2018 New Revision: 266870 URL: https://gcc.gnu.org/viewcvs?rev=266870=gcc=rev Log: [rs6000] Enable x86-compat vector intrinsics testing The testsuite tests for the compatibility implementations of x86 vector intrinsics for "powerpc" had been inadvertently made to PASS without actually running the test code. This patch removes the code which kept the tests from running the actual test code. 2018-12-06 Paul A. Clarke [gcc/testsuite] PR target/88316 * gcc.target/powerpc/bmi-check.h: Remove test for __BUILTIN_CPU_SUPPORTS__, thereby enabling test code to run. * gcc.target/powerpc/bmi2-check.h: Likewise. * gcc.target/powerpc/mmx-check.h: Likewise. * gcc.target/powerpc/sse-check.h: Likewise. * gcc.target/powerpc/sse2-check.h: Likewise. * gcc.target/powerpc/sse3-check.h: Likewise. Modified: trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/powerpc/bmi-check.h trunk/gcc/testsuite/gcc.target/powerpc/bmi2-check.h trunk/gcc/testsuite/gcc.target/powerpc/mmx-check.h trunk/gcc/testsuite/gcc.target/powerpc/sse-check.h trunk/gcc/testsuite/gcc.target/powerpc/sse2-check.h trunk/gcc/testsuite/gcc.target/powerpc/sse3-check.h
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 --- Comment #2 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 6 22:11:01 2018 New Revision: 266869 URL: https://gcc.gnu.org/viewcvs?rev=266869=gcc=rev Log: [rs6000] Fix x86-compat vector intrinsics testcases for BE, 32bit Fix general endian issues found in the test cases for thecompatibility implementations of the x86 vector intrinsics. (The tests had been inadvertently made to PASS without actually running the test code. A later patch fixes this issue.) Additionally, a new is added, as some of the APIs therein are now used by the test cases. It is _not_ a complete implementation of the SSE4 interfaces, only the few "extract" interfaces uses by the tests. 2018-12-06 Paul A. Clarke [gcc] PR target/88316 * config/rs6000/smmintrin.h: New file. * config.gcc: Add smmintrin.h to extra_headers for powerpc*-*-*. [gcc/testsuite] PR target/88316 * gcc.target/powerpc/mmx-packssdw-1.c: Fixes for big-endian. * gcc.target/powerpc/mmx-packsswb-1.c: Likewise. * gcc.target/powerpc/mmx-packuswb-1.c: Likewise. * gcc.target/powerpc/mmx-pmulhw-1.c: Likewise. * gcc.target/powerpc/sse-cvtpi32x2ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtpu16ps-1.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-1.c: Likewise. * gcc.target/powerpc/sse-cvtss2si-2.c: Likewise. * gcc.target/powerpc/sse2-pshufhw-1.c: Likewise. * gcc.target/powerpc/sse2-pshuflw-1.c: Likewise. Added: trunk/gcc/config/rs6000/smmintrin.h Modified: trunk/gcc/ChangeLog trunk/gcc/config.gcc trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/powerpc/mmx-packssdw-1.c trunk/gcc/testsuite/gcc.target/powerpc/mmx-packsswb-1.c trunk/gcc/testsuite/gcc.target/powerpc/mmx-packuswb-1.c trunk/gcc/testsuite/gcc.target/powerpc/mmx-pmulhw-1.c trunk/gcc/testsuite/gcc.target/powerpc/sse-cvtpi32x2ps-1.c trunk/gcc/testsuite/gcc.target/powerpc/sse-cvtpu16ps-1.c trunk/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-1.c trunk/gcc/testsuite/gcc.target/powerpc/sse-cvtss2si-2.c trunk/gcc/testsuite/gcc.target/powerpc/sse2-pshufhw-1.c trunk/gcc/testsuite/gcc.target/powerpc/sse2-pshuflw-1.c
[Bug target/88316] numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316 --- Comment #1 from pc at gcc dot gnu.org --- Author: pc Date: Thu Dec 6 22:03:25 2018 New Revision: 266868 URL: https://gcc.gnu.org/viewcvs?rev=266868=gcc=rev Log: [rs6000] x86-compat vector intrinsics fixes for BE, 32bit Fix general endian and 32-bit mode issues found in the compatibility implementations of the x86 vector intrinsics when running the associated test suite tests. (The tests had been inadvertently made to PASS without actually running the test code. A later patch fixes this issue.) 2018-12-03 Paul A. Clarke PR target/88316 * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. (_mm_unpacklo_pi8): Likewise. (_mm_mulhi_pi16): Likewise. (_mm_packs_pi16): Fix for big-endian. Use preferred API. (_mm_packs_pi32): Likewise. (_mm_packs_pu16): Likewise. * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. (_mm_cvtss_si64): Likewise. (_mm_cvtpi32x2_ps): Likewise. (_mm_shuffle_ps): Likewise. (_mm_movemask_pi8): Likewise. (_mm_mulhi_pu16): Likewise. (_mm_sad_pu8): Likewise. (_mm_sad_pu8): Likewise. (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. (_mm_cvtpu8_ps): Likewise. (_mm_movemask_ps): Better #else case for big-endian (no functional change). (_mm_shuffle_pi16): Likewise. * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. Better #else case for big-endian (no functional change). (_mm_movemask_epi8): Likewise. (_mm_shufflehi_epi16): Likewise. (_mm_shufflelo_epi16): Likewise. (_mm_shuffle_epi32): Likewise. (_mm_mul_epu32): Fix for big-endian. (_mm_bsrli_si128): Likewise. (_mm_cvtps_pd): Better #else case for big endian. (_mm_mulhi_epi16): Likewise. (_mm_mul_epu32): Likewise. (_mm_slli_si128): Likewise. (_mm_sll_epi16): Likewise. (_mm_sll_epi32): Likewise. (_mm_sra_epi16): Likewise. (_mm_sra_epi32): Likewise. (_mm_srl_epi16): Likewise. (_mm_srl_epi32): Likewise. (_mm_mulhi_epu16): Likewise. (_mm_sad_epu8): Likewise. * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. (_mm_sub_ps): Likewise. * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. * gcc/config/rs6000/tmmintrin.h (_mm_alignr_epi8): Use ENDIAN macros consistently (no functional changes). (_mm_alignr_pi8): Likewise. Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/emmintrin.h trunk/gcc/config/rs6000/mmintrin.h trunk/gcc/config/rs6000/pmmintrin.h trunk/gcc/config/rs6000/tmmintrin.h trunk/gcc/config/rs6000/xmmintrin.h
[Bug target/88316] New: numerous big-endian issues with compatibility implementations of vector intrinsics for powerpc
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88316
Bug ID: 88316
Summary: numerous big-endian issues with compatibility
implementations of vector intrinsics for powerpc
Product: gcc
Version: 9.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pc at gcc dot gnu.org
Target Milestone: ---
Many of the test cases for the compatibility implementations of x86 vector
intrinsics for powerpc were structured like:
--
int
main ()
{
#ifdef __BUILTIN_CPU_SUPPORTS__
/* testing code */
#endif /* __BUILTIN_CPU_SUPPORTS__ */
return 0;
}
--
...which had the unfortunate side-effect of allowing all such tests to silently
pass without actually testing anything. Removing the protective #ifdef permits
the tests to run, which has the unfortunate side-effect of exposing a raft of
big-endian (and 32bit mode) bugs.
I will tackle these en-masse.
[Bug target/88100] New: no warning reported when value for vec_splat_{su}{8,16} would overflow
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88100
Bug ID: 88100
Summary: no warning reported when value for
vec_splat_{su}{8,16} would overflow
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: pc at gcc dot gnu.org
Target Milestone: ---
Created attachment 45036
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=45036=edit
test case
$ cat bug.c
#include
void foo() {
signed char cs0 = 0x100;
unsigned char cu0= 0x100;
signed short ss0 = 0x1;
unsigned short su0= 0x1;
signed int is0 = 0x1;
unsigned int iu0= 0x1;
vector signed char v8 = vec_splat_s8(256);
vector unsigned char v11 = vec_splat_u8(256);
vector signed short v12 = vec_splat_s16(0x1);
vector unsigned short v13 = vec_splat_u16(0x1);
vector signed int v14 = vec_splat_s32(0x1);
vector unsigned int v15 = vec_splat_u32(0x1);
}
$ gcc -c bug.c
bug.c: In function ‘foo’:
bug.c:3:21: warning: overflow in conversion from ‘int’ to ‘signed char’ changes
value from ‘256’ to ‘0’ [-Woverflow]
signed char cs0 = 0x100;
^
bug.c:4:22: warning: unsigned conversion from ‘int’ to ‘unsigned char’ changes
value from ‘256’ to ‘0’ [-Woverflow]
unsigned char cu0= 0x100;
^
bug.c:5:22: warning: overflow in conversion from ‘int’ to ‘short int’ changes
value from ‘65536’ to ‘0’ [-Woverflow]
signed short ss0 = 0x1;
^~~
bug.c:6:23: warning: unsigned conversion from ‘int’ to ‘short unsigned int’
changes value from ‘65536’ to ‘0’ [-Woverflow]
unsigned short su0= 0x1;
^~~
bug.c:7:20: warning: overflow in conversion from ‘long int’ to ‘int’ changes
value from ‘4294967296’ to ‘0’ [-Woverflow]
signed int is0 = 0x1;
^~~
bug.c:8:21: warning: unsigned conversion from ‘long int’ to ‘unsigned int’
changes value from ‘4294967296’ to ‘0’ [-Woverflow]
unsigned int iu0= 0x1;
^~~
bug.c:13:27: warning: overflow in conversion from ‘long int’ to ‘int’ changes
value from ‘4294967296’ to ‘0’ [-Woverflow]
vector signed int v14 = vec_splat_s32(0x1);
^
bug.c:14:29: warning: overflow in conversion from ‘long int’ to ‘int’ changes
value from ‘4294967296’ to ‘0’ [-Woverflow]
vector unsigned int v15 = vec_splat_u32(0x1);
^
--
Note: no warnings for the vector char and vector short types.
[Bug target/87579] new powerpc64 sse3 test cases in r264992 have compilation failures
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87579
pc at gcc dot gnu.org changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|--- |FIXED
--- Comment #4 from pc at gcc dot gnu.org ---
$ svn info
Path: .
Working Copy Root Path: /home/pc/trunk
URL: svn+ssh://p...@gcc.gnu.org/svn/gcc/trunk
Repository Root: svn+ssh://p...@gcc.gnu.org/svn/gcc
Repository UUID: 138bc75d-0d04-0410-961f-82ee72b054a4
Revision: 265026
Node Kind: directory
Schedule: normal
Last Changed Author: pc
Last Changed Rev: 265026
Last Changed Date: 2018-10-10 15:52:48 -0500 (Wed, 10 Oct 2018)
$ make -k check-gcc-c RUNTESTFLAGS="--target_board=unix'{-m32,-m64}'
powerpc.exp=pr37191*"
...
=== gcc Summary ===
# of expected passes1
# of unsupported tests 1
$ make -k check-gcc-c RUNTESTFLAGS="--target_board=unix'{-m32,-m64}'
powerpc.exp=sse3*"
...
=== gcc Summary ===
# of expected passes20
# of unsupported tests 10
[Bug target/87579] new powerpc64 sse3 test cases in r264992 have compilation failures
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87579 --- Comment #3 from pc at gcc dot gnu.org --- Author: pc Date: Wed Oct 10 20:52:48 2018 New Revision: 265026 URL: https://gcc.gnu.org/viewcvs?rev=265026=gcc=rev Log: Fat-fingered my recent patch adding the SSE3 testcases for powerpc, most likely by twice applying the patch which added the testcases. This patch removes the duplicated code. [gcc/testsuite] 2018-10-10 Paul A. Clarke PR target/87579 * gcc.target/powerpc/sse3-check.h: Remove duplicated code. * gcc.target/powerpc/sse3-addsubps.c: Likewise. * gcc.target/powerpc/sse3-addsubpd.c: Likewise. * gcc.target/powerpc/sse3-haddps.c: Likewise. * gcc.target/powerpc/sse3-hsubps.c: Likewise. * gcc.target/powerpc/sse3-haddpd.c: Likewise. * gcc.target/powerpc/sse3-hsubpd.c: Likewise. * gcc.target/powerpc/sse3-lddqu.c: Likewise. * gcc.target/powerpc/sse3-movsldup.c: Likewise. * gcc.target/powerpc/sse3-movshdup.c: Likewise. * gcc.target/powerpc/sse3-movddup.c: Likewise. * gcc.target/powerpc/pr37191.c: Likewise. Modified: trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/powerpc/pr37191.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-addsubpd.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-addsubps.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-check.h trunk/gcc/testsuite/gcc.target/powerpc/sse3-haddpd.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-haddps.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-hsubpd.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-hsubps.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-lddqu.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-movddup.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-movshdup.c trunk/gcc/testsuite/gcc.target/powerpc/sse3-movsldup.c
[Bug target/87579] new powerpc64 sse3 test cases in r264992 have compilation failures
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87579 --- Comment #2 from pc at gcc dot gnu.org --- The patch for these changes was inadvertently applied twice before being committed, resulting in duplicated code in the new files. I will check in a patch shortly to remove the extra code.
[Bug target/83402] PPC64 implementation of ./rs6000/emmintrin.h gives out of range for _mm_slli_epi32
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83402
--- Comment #15 from pc at gcc dot gnu.org ---
Author: pc
Date: Mon Apr 23 21:14:38 2018
New Revision: 259582
URL: https://gcc.gnu.org/viewcvs?rev=259582=gcc=rev
Log:
rs6000: Fix _mm_slli_epi{32,64} for shift values 16 through 31 and negative
(PR84302)
The powerpc versions of _mm_slli_epi32 and __mm_slli_epi64 in emmintrin.h
do not properly handle shift values between 16 and 31, inclusive.
These are setting up the shift with vec_splat_s32, which only accepts
*5 bit signed* shift values, or a range of -16 to 15. Values above 15
produce an error:
error: argument 1 must be a 5-bit signed literal
Fix is to effectively reduce the range for which vec_splat_s32 is used
to < 32 and use vec_splats otherwise.
Also, __mm_slli_epi{16,32,64}, when given a negative shift value,
should always return a vector of {0}.
PR target/83402
* config/rs6000/emmintrin.h (_mm_slli_epi{16,32,64}):
Ensure that vec_splat_s32 is only called with 0 <= shift < 16.
Ensure negative shifts result in {0}.
gcc/testsuite/
PR target/83402
* gcc.target/powerpc/sse2-psllw-1.c: Refactor and add tests for
several values: positive, negative, and zero.
* gcc.target/powerpc/sse2-pslld-1.c: Same.
* gcc.target/powerpc/sse2-psllq-1.c: Same.
Modified:
branches/ibm/gcc-7-branch/gcc/ChangeLog
branches/ibm/gcc-7-branch/gcc/config/rs6000/emmintrin.h
branches/ibm/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/sse2-pslld-1.c
branches/ibm/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/sse2-psllq-1.c
branches/ibm/gcc-7-branch/gcc/testsuite/gcc.target/powerpc/sse2-psllw-1.c
