https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108891
Bug ID: 108891 Summary: libatomic: AArch64 SEQ_CST 16-byte load missing barrier Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: libgcc Assignee: unassigned at gcc dot gnu.org Reporter: wilco at gcc dot gnu.org Target Milestone: --- LSE2 uses the following sequence for a 16-byte atomic load: ldp res0, res1, [x0] dmb ish The AArch64 memory model allows the LDP to be reordered with an earlier STLXP (eg. a SEQ_CST exchange), thus breaking SEQ_CST ordering. To avoid this, atomic loads need a barrier before the LDP - either DBM ISHLD or LDAR works.