[Bug middle-end/107991] [10/11/12/13 Regression] Extra mov instructions with ternary on x86

2023-01-09 Thread roger at nextmovesoftware dot com via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107991

Roger Sayle  changed:

   What|Removed |Added

 CC||roger at nextmovesoftware dot 
com

--- Comment #6 from Roger Sayle  ---
An x86 peephole2 to workaround the problem was proposed here:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609578.html
but improved register allocation (if possible) would be a better solution:
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609588.html

[Bug middle-end/107991] [10/11/12/13 Regression] Extra mov instructions with ternary on x86

2022-12-21 Thread rsandifo at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107991

--- Comment #5 from rsandifo at gcc dot gnu.org  
---
>From a slightly old build, but it looks like we have a redundant move:

(insn 4 27 28 2 (set (reg/v:SI 85 [ i ])
(reg:SI 91)) "foo.c":9:31 83 {*movsi_internal}
 (expr_list:REG_DEAD (reg:SI 91)
(nil)))

This causes problems because we can then assign different preferences
and costs to 85 and 91.  91 comes from input register SI and so prefers
SIREG while 85 feeds the result and so prefers AREG.

We should be able to cope better with this, will have a look in the new
year.

The output seems better with -fweb.

[Bug middle-end/107991] [10/11/12/13 Regression] Extra mov instructions with ternary on x86

2022-12-21 Thread rguenth at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107991

Richard Biener  changed:

   What|Removed |Added

   Priority|P3  |P2
   Keywords|needs-bisection |

--- Comment #4 from Richard Biener  ---
Martins change doesn't look very related to me, Richards one does though.

[Bug middle-end/107991] [10/11/12/13 Regression] Extra mov instructions with ternary on x86

2022-12-08 Thread jakub at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107991

Jakub Jelinek  changed:

   What|Removed |Added

 CC||jakub at gcc dot gnu.org,
   ||marxin at gcc dot gnu.org,
   ||rsandifo at gcc dot gnu.org

--- Comment #3 from Jakub Jelinek  ---
2 mov insns in foo/bar instead of 1 started with
r8-1519-ge59a1c22fb249388e82b4fd004f33615abe36d2e PR79489 fix.
And 3 mov insns in all 3 instead of 2 started with the
r10-3679-g9b0365879b3c4917f5a2485a1fca8bb678484bfe change.

[Bug middle-end/107991] [10/11/12/13 Regression] Extra mov instructions with ternary on x86

2022-12-06 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107991

Andrew Pinski  changed:

   What|Removed |Added

  Known to fail||8.1.0
  Component|rtl-optimization|middle-end

--- Comment #2 from Andrew Pinski  ---
The huge difference comes from the middle-end:
Trunk (and not working):
(insn 12 11 13 4 (parallel [
(set (reg/v:SI 85 [ i ])
(minus:SI (reg/v:SI 85 [ i ])
(reg/v:SI 86 [ j ])))
(clobber (reg:CC 17 flags))
]) "/app/example.cpp":2:14 discrim 1 -1
 (nil))

vs 7.5 (working case):
(insn 13 12 22 4 (parallel [
(set (reg:SI 87 [  ])
(minus:SI (reg/v:SI 90 [ i ])
(reg/v:SI 91 [ j ])))
(clobber (reg:CC 17 flags))
]) "/app/example.cpp":2 -1
 (nil))

that is coalescing the PHI node:
  # iftmp.0_1 = PHI 

to i rather than inserting a setting on the other branch.