[Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts

2023-10-09 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743

--- Comment #6 from Andrew Pinski  ---
(In reply to Andi Kleen from comment #5)
> config/i386/i386.h:#define SLOW_BYTE_ACCESS 0
> 
> You mean it doesn't define it?

The default is 1.
Anyways in this case I was wrong but defining it to 0 causes other issues.

[Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts

2023-10-09 Thread andi-gcc at firstfloor dot org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743

--- Comment #5 from Andi Kleen  ---

config/i386/i386.h:#define SLOW_BYTE_ACCESS 0

You mean it doesn't define it?

[Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts

2023-10-09 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743

Andrew Pinski  changed:

   What|Removed |Added

   See Also||https://gcc.gnu.org/bugzill
   ||a/show_bug.cgi?id=107601

--- Comment #4 from Andrew Pinski  ---
x86_64 defines SLOW_BYTE_ACCESS which caues some (if not all) of the issues
here:
```
;; _3 = bf.c;

(insn 9 8 10 (parallel [
(set (reg:DI 106)
(lshiftrt:DI (reg/v:DI 104 [ bf ])
(const_int 32 [0x20])))
(clobber (reg:CC 17 flags))
]) "/app/example.cpp":5:58 -1
 (nil))

(insn 10 9 0 (parallel [
(set (reg:HI 100 [ _3 ])
(and:HI (subreg:HI (reg:DI 106) 0)
(const_int 1023 [0x3ff])))
(clobber (reg:CC 17 flags))
]) "/app/example.cpp":5:58 -1
 (nil))

;; _4 = (unsigned int) _3;

(insn 11 10 0 (set (reg:SI 101 [ _4 ])
(zero_extend:SI (reg:HI 100 [ _3 ]))) "/app/example.cpp":5:46 -1
 (nil))
```
Uses HImode (short) here due to SLOW_BYTE_ACCESS being defined rather than the
SImode (int).

[Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts

2023-10-09 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743

Andrew Pinski  changed:

   What|Removed |Added

 Ever confirmed|0   |1
 CC||pinskia at gcc dot gnu.org
   Severity|normal  |enhancement
   Last reconfirmed||2023-10-09
 Status|UNCONFIRMED |NEW

--- Comment #3 from Andrew Pinski  ---
RTL wise we have:
Trying 6, 8 -> 9:
6: {r108:DI=r105:DI 0>>0x20;clobber flags:CC;}
  REG_UNUSED flags:CC
8: {r110:SI=r108:DI#0&0x3ff;clobber flags:CC;}
  REG_UNUSED flags:CC
  REG_DEAD r108:DI
9: {r111:SI=r110:SI<<0x14;clobber flags:CC;}
  REG_DEAD r110:SI
  REG_UNUSED flags:CC
Failed to match this instruction:
(parallel [
(set (reg:SI 111)
(and:SI (ashift:SI (subreg:SI (zero_extract:DI (reg/v:DI 105 [ bf
])
(const_int 32 [0x20])
(const_int 32 [0x20])) 0)
(const_int 20 [0x14]))
(const_int 1072693248 [0x3ff0])))
(clobber (reg:CC 17 flags))
])

This should have been simplified.
Anyways bitfields have issues even on the gimple level as they are not lowered
until expand ...

[Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts

2023-10-09 Thread andi-gcc at firstfloor dot org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743

--- Comment #2 from Andi Kleen  ---
Okay then it doesn't understand that SHL_signed and SHR_unsigned can be
combined when one the values came from a shorter unsigned.

[Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts

2023-10-09 Thread pinskia at gcc dot gnu.org via Gcc-bugs 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743

--- Comment #1 from Andrew Pinski  ---
Remember types smaller than int is prompted to int .