--- Comment #6 from manu at gcc dot gnu dot org 2007-11-13 04:36 ---
Most of the typos are gone. And updated patch:
Index: gcc/doc/passes.texi
===
--- gcc/doc/passes.texi (revision 130092)
+++ gcc/doc/passes.texi (working copy)
@@ -490,7 +490,7 @@
@item Folding built-in functions
This pass simplifies built-in functions, as applicable, with constant
-arguments or with inferrable string lengths. It is located in
+arguments or with inferable string lengths. It is located in
@file{tree-ssa-ccp.c} and is described by @code{pass_fold_builtins}.
@item Split critical edges
Index: gcc/doc/invoke.texi
===
--- gcc/doc/invoke.texi (revision 130092)
+++ gcc/doc/invoke.texi (working copy)
@@ -1786,7 +1786,7 @@
of the language, you can save some space by using this flag. Note that
exception handling uses the same information, but it will generate it as
needed. The @samp{dynamic_cast} operator can still be used for casts that
-do not require runtime type information, i.e. casts to @code{void *} or to
+do not require runtime type information, i.e., casts to @code{void *} or to
unambiguous base classes.
@item -fstats
@@ -6716,7 +6716,7 @@
For small units this might be too tight (consider unit consisting of function
A
that is inline and B that just calls A three time. If B is small relative to
A, the growth of unit is 300\% and yet such inlining is very sane. For very
-large units consisting of small inlininable functions however the overall unit
+large units consisting of small inlineable functions however the overall unit
growth limit is needed to avoid exponential explosion of code size. Thus for
smaller units, the size is increased to @option{--param large-unit-insns}
before applying @option{--param inline-unit-growth}. The default is 1
@@ -7077,7 +7077,7 @@
@item integer-share-limit
Small integer constants can use a shared data structure, reducing the
compiler's memory usage and increasing its speed. This sets the maximum
-value of a shared integer constant's. The default value is 256.
+value of a shared integer constant. The default value is 256.
@item min-virtual-mappings
Specifies the minimum number of virtual mappings in the incremental
@@ -7092,7 +7092,7 @@
ratio is 3.
@item ssp-buffer-size
-The minimum size of buffers (i.e. arrays) that will receive stack smashing
+The minimum size of buffers (i.e., arrays) that will receive stack smashing
protection when @option{-fstack-protection} is used.
@item max-jump-thread-duplication-stmts
@@ -10049,7 +10049,7 @@
@option{--with-ld} configure option, GCC's program search path, and
finally by the user's @env{PATH}. The linker used by GCC can be printed
using @samp{which `gcc -print-prog-name=ld`}. This option is only available
-on the 64 bit HP-UX GCC, i.e. configured with @samp{hppa*64*-*-hpux*}.
+on the 64 bit HP-UX GCC, i.e., configured with @samp{hppa*64*-*-hpux*}.
@item -mhp-ld
@opindex hp-ld
@@ -10062,7 +10062,7 @@
configure option, GCC's program search path, and finally by the user's
@env{PATH}. The linker used by GCC can be printed using @samp{which
`gcc -print-prog-name=ld`}. This option is only available on the 64 bit
-HP-UX GCC, i.e. configured with @samp{hppa*64*-*-hpux*}.
+HP-UX GCC, i.e., configured with @samp{hppa*64*-*-hpux*}.
@item -mlong-calls
@opindex mno-long-calls
@@ -10219,16 +10219,16 @@
@item k6
AMD K6 CPU with MMX instruction set support.
@item k6-2, k6-3
-Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support.
+Improved versions of AMD K6 CPU with MMX and 3dNOW!@: instruction set support.
@item athlon, athlon-tbird
-AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions
+AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and SSE prefetch
instructions
support.
@item athlon-4, athlon-xp, athlon-mp
-Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
+Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW!@: and full SSE
instruction set support.
@item k8, opteron, athlon64, athlon-fx
AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
-MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set
extensions.)
+MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW!@: and 64-bit instruction set
extensions.)
@item k8-sse3, opteron-sse3, athlon64-sse3
Improved versions of k8, opteron and athlon64 with SSE3 instruction set
support.
@item amdfam10, barcelona
@@ -10239,10 +10239,10 @@
IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.
@item winchip2
-IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
+IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!@:
instruction set support.
@item c3
-Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
+Via C3 CPU with
