[Bug rtl-optimization/104664] [12 Regression] ICE: in extract_constrain_insn, at recog.cc:2670 (insn does not satisfy its constraints) with -Og -ffinite-math-only

[wwwhhhyyy333 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104664

--- Comment #6 from Hongyu Wang  ---
Fixed for GCC 12.

[Bug rtl-optimization/104664] [12 Regression] ICE: in extract_constrain_insn, at recog.cc:2670 (insn does not satisfy its constraints) with -Og -ffinite-math-only

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104664

--- Comment #5 from CVS Commits  ---
The master branch has been updated by Hongyu Wang :

https://gcc.gnu.org/g:e2385690a3ead66744e51115966f25f9c05bb3e2

commit r12-7419-ge2385690a3ead66744e51115966f25f9c05bb3e2
Author: Hongyu Wang 
Date:   Mon Feb 28 15:09:59 2022 +0800

i386: Fix V8HF vector init under -mno-avx [PR 104664]

For V8HFmode vector init with HFmode, do not directly emits V8HF move
with subreg, which may cause reload to assign general register to move
src.

gcc/ChangeLog:

PR target/104664
* config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate):
  Use vec_setv8hf_0 for HF to V8HFmode move instead of subreg.

gcc/testsuite/ChangeLog:

PR target/104664
* gcc.target/i386/pr104664.c: New test.

[Bug rtl-optimization/104664] [12 Regression] ICE: in extract_constrain_insn, at recog.cc:2670 (insn does not satisfy its constraints) with -Og -ffinite-math-only

[wwwhhhyyy333 at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104664

--- Comment #4 from Hongyu Wang  ---
(In reply to Uroš Bizjak from comment #3)

> Reconfirmed as RA issue.

I'm afraid we'd avoid pattern like

(insn 180 179 182 2 (set (reg:V8HF 220)
(subreg:V8HF (reg:HF 221) 0)) "pr104664.c":12:7 1710 {movv8hf_internal}

since we don't have corresponding pattern with subreg. Reload might not aware
of the newly inserted regs properly, as the message shows

Set class ALL_REGS for r221
Set class ALL_REGS for r220

I'm testing

diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 6cf1a0b9cb6..658516d86a2 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -14883,7 +14883,12 @@ ix86_expand_vector_init_duplicate (bool mmx_ok,
machine_mode mode,
  dperm.one_operand_p = true;

  if (mode == V8HFmode)
-   tmp1 = lowpart_subreg (V8HFmode, force_reg (HFmode, val), HFmode);  
+   {
+ tmp1 = force_reg (HFmode, val);
+ tmp2 = gen_reg_rtx (mode);
+ emit_insn (gen_vec_setv8hf_0 (tmp2, CONST0_RTX (mode), tmp1));
+ tmp1 = gen_lowpart (mode, tmp2);
+   }

[Bug rtl-optimization/104664] [12 Regression] ICE: in extract_constrain_insn, at recog.cc:2670 (insn does not satisfy its constraints) with -Og -ffinite-math-only

[ubizjak at gmail dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104664

Uroš Bizjak  changed:

   What|Removed |Added

   Keywords||ra
  Component|target  |rtl-optimization

--- Comment #3 from Uroš Bizjak  ---
Reload wants to generate (-mavx2) the following reload for (insn 28):

   28: r127:HF=vec_select(r217:V8HF,parallel)
Inserting insn reload before:
  177: r218:V8HF=vec_duplicate([`*.LC1'])
  178: r217:V8HF=r218:V8HF

But without -mavx2 it generates:

   28: r217:HF=vec_select(r218:V8HF,parallel)
Inserting insn reload before:
  179: r221:HF=[`*.LC1']
  180: r220:V8HF=r221:HF#0
  182: r222:V8HF=vec_select(vec_concat(r220:V8HF,r220:V8HF),parallel)
  183: r223:V4SI=vec_select(r222:V8HF#0,parallel)
  184: r219:V8HF=r223:V4SI#0
  185: r218:V8HF=r219:V8HF
Inserting insn reload after:
  178: r127:HF=r217:HF

where:

 Choosing alt 2 in insn 179:  (0) ?r  (1) m {*movhf_internal}
 Choosing alt 2 in insn 180:  (0) v  (1) vm {movv8hf_internal}

The allocator could choose alternative 9 (v,m) in:

(define_insn "*movhf_internal"
 [(set (match_operand:HF 0 "nonimmediate_operand"
 "=?r,?r,?r,?m,v,v,?r,m,?v,v")
   (match_operand:HF 1 "general_operand"
 "r  ,F ,m ,rF,C,v, v,v,r ,m"))]

Since xmm registers support HF and V8HF modes.

Reconfirmed as RA issue.