[Bug rtl-optimization/107949] PPC: Unnecessary rlwinm after lbzx
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 --- Comment #6 from Segher Boessenkool --- We generate loads into QImode regs, so we need to explicitly convert it to whatever larger mode is wanted later. We also have define_insns to do a zero-extended load directly into a bigger pseudo, but that isn't used apparently. This is one instance of a much more generic problem; on rs6000 this is usually observed as SImode being extended to DImode more often than needed / wanted.
[Bug rtl-optimization/107949] PPC: Unnecessary rlwinm after lbzx
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 Peter Bergner changed: What|Removed |Added CC||bergner at gcc dot gnu.org --- Comment #5 from Peter Bergner --- (In reply to Segher Boessenkool from comment #4) > How would GCC know no extension is needed? The asm template is not parsed > at all, by design. Making h1 an unsigned char might solve it here? The version with the inline asm isn't what Jens is worried about, that gives the generated code he wants (ie, no rlwinm). He asking why the fully C version of the test case adds the unneeded rlwinm.
[Bug rtl-optimization/107949] PPC: Unnecessary rlwinm after lbzx
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 Segher Boessenkool changed: What|Removed |Added CC||segher at gcc dot gnu.org --- Comment #4 from Segher Boessenkool --- How would GCC know no extension is needed? The asm template is not parsed at all, by design. Making h1 an unsigned char might solve it here?
[Bug rtl-optimization/107949] PPC: Unnecessary rlwinm after lbzx
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949 --- Comment #3 from Jens Seifert --- *** Bug 108048 has been marked as a duplicate of this bug. ***
[Bug rtl-optimization/107949] PPC: Unnecessary rlwinm after lbzx
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107949
Andrew Pinski changed:
What|Removed |Added
Last reconfirmed||2022-12-02
Component|target |rtl-optimization
Target|powerpc |powerpc, aarch64
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
--- Comment #2 from Andrew Pinski ---
aarch64 has the same issue (with almost the same RTL even)
(insn 6 3 7 2 (set (reg:QI 123 [ *inp_5(D) ])
(mem:QI (reg/v/f:SI 121 [ inp ]) [0 *inp_5(D)+0 S1 A8]))
"/app/example.cpp":4:17 554 {*movqi_internal}
(nil))
(insn 7 6 8 2 (set (reg:QI 124 [ MEM[(const unsigned char *)inp_5(D) + 1B] ])
(mem:QI (plus:SI (reg/v/f:SI 121 [ inp ])
(const_int 1 [0x1])) [0 MEM[(const unsigned char *)inp_5(D) +
1B]+0 S1 A8])) "/app/example.cpp":4:17 554 {*movqi_internal}
(expr_list:REG_DEAD (reg/v/f:SI 121 [ inp ])
(nil)))
(insn 8 7 9 2 (set (reg:SI 125)
(xor:SI (subreg:SI (reg:QI 123 [ *inp_5(D) ]) 0)
(subreg:SI (reg:QI 124 [ MEM[(const unsigned char *)inp_5(D) + 1B]
]) 0))) "/app/example.cpp":4:17 215 {*boolsi3}
(expr_list:REG_DEAD (reg:QI 124 [ MEM[(const unsigned char *)inp_5(D) +
1B] ])
(expr_list:REG_DEAD (reg:QI 123 [ *inp_5(D) ])
(nil
(note 9 8 21 2 NOTE_INSN_DELETED)
(insn 21 9 22 2 (set (reg:SI 3 3)
(const_int 0 [0])) "/app/example.cpp":5:1 549 {*movsi_internal1}
(nil))
(insn 22 21 17 2 (set (reg:SI 4 4 [orig:3+4 ] [3])
(zero_extend:SI (subreg:QI (reg:SI 125) 3))) "/app/example.cpp":5:1 4
{zero_extendqisi2}
(expr_list:REG_DEAD (reg:SI 125)
(nil)))
We lose track (didn't take into account LOAD_EXTEND_OP(QImode) is ZERO_EXTEND
?) that the memory was zero extended.
