[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 Li Pan changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #8 from Li Pan --- Fixed.
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 --- Comment #7 from GCC Commits --- The master branch has been updated by Dimitar Dimitrov : https://gcc.gnu.org/g:fc559584fa5b1e101a4520e88a936246458d5a5d commit r15-493-gfc559584fa5b1e101a4520e88a936246458d5a5d Author: Dimitar Dimitrov Date: Mon May 13 19:24:14 2024 +0300 pru: Implement TARGET_CLASS_LIKELY_SPILLED_P to fix PR115013 Commit r15-436-g44e7855e did not fix PR115013 for PRU because SMALL_REGISTER_CLASS_P is not returning an accurate value for the PRU backend. Word mode for PRU backend is defined as 8-bit, yet all ALU operations are preferred in 32-bit mode. Thus checking whether a register class contains a single word_mode register would not classify the actually single SImode register classes as small. This affected the multiplication source and destination register classes. Fix by implementing TARGET_CLASS_LIKELY_SPILLED_P to treat all register classes with SImode or smaller size as likely spilled. This in turn corrects the behaviour of SMALL_REGISTER_CLASS_P for PRU. PR rtl-optimization/115013 gcc/ChangeLog: * config/pru/pru.cc (pru_class_likely_spilled_p): Implement to mark classes containing one SImode register as likely spilled. (TARGET_CLASS_LIKELY_SPILLED_P): Define. Signed-off-by: Dimitar Dimitrov
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 --- Comment #6 from Dimitar Dimitrov --- Created attachment 58194 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=58194=edit tentative fix for PRU The PRU requires a further target adjustment to fix SMALL_REGISTER_CLASS_P. The attached patch fixes the dg.exp=pr71478.c regression. I'm doing full regression tests now, and will commit if there are no objections.
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 --- Comment #5 from Jeffrey A. Law --- So this seems to have fixed the RISC-V port. Thanks! I'm still seeing some problems on the PRU port though: Tests that now fail, but worked before (1 tests): pru-sim: gcc: gcc.dg/pr71478.c (test for excess errors) New tests that FAIL (1 tests): pru-sim: gcc: gcc.dg/pr71478.c (internal compiler error: in lra_split_hard_reg_for, at lra-assigns.cc:1868) New tests that PASS (1 tests): pru-sim: gcc: gcc.dg/pr113982.c (test for excess errors)
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 --- Comment #4 from GCC Commits --- The master branch has been updated by Vladimir Makarov : https://gcc.gnu.org/g:44e7855e4e817a7f5a1e332cd95e780e57052dba commit r15-436-g44e7855e4e817a7f5a1e332cd95e780e57052dba Author: Vladimir N. Makarov Date: Mon May 13 10:12:11 2024 -0400 [PR115013][LRA]: Modify register starvation recognition My recent patch to recognize reg starvation resulted in few GCC test failures. The following patch fixes this by using more accurate starvation calculation and ignoring small reg classes. gcc/ChangeLog: PR rtl-optimization/115013 * lra-constraints.cc (process_alt_operands): Update all_used_nregs only for winreg. Ignore reg starvation for small reg classes.
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 Jeffrey A. Law changed: What|Removed |Added Status|UNCONFIRMED |NEW Ever confirmed|0 |1 Last reconfirmed||2024-05-10 --- Comment #3 from Jeffrey A. Law --- No worries Vlad. At least for my tester I've got the LRA patch reverted. So I'm getting regular test results. Thanks for diving in and for the review work on the Rivai's team on subreg tracking in the allocator.
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 Vladimir Makarov changed: What|Removed |Added CC||vmakarov at gcc dot gnu.org --- Comment #2 from Vladimir Makarov --- Sorry for troubles. I've started to work on this PR. ETA for the fix is Monday.
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Jeffrey A. Law changed:
What|Removed |Added
CC||law at gcc dot gnu.org
Target|RISC-V |RISC-V, pru
--- Comment #1 from Jeffrey A. Law ---
The LRA patch has also been identified as the cause of similar failures in the
PRU port (gcc.dg/pr71478.c):
/cc1 -O2 pr71478.c -quiet
pr71478.c: In function ‘foo’:
pr71478.c:19:1: error: unable to find a register to spill
19 | }
| ^
pr71478.c:19:1: error: this is the insn:
(insn 15 33 30 2 (set (reg:SI 169 [orig:163 _11 ] [163])
(mult:SI (reg:SI 171)
(reg:SI 172 [170]))) "pr71478.c":18:12 discrim 1 631 {mulsi3}
(expr_list:REG_DEAD (reg:SI 172 [170])
(expr_list:REG_DEAD (reg:SI 171)
(nil
during RTL pass: reload
pr71478.c:19:1: internal compiler error: in lra_split_hard_reg_for, at
lra-assigns.cc:1868
0x14fda20 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
/home/jlaw/test/gcc/gcc/rtl-error.cc:108
0x12eff3a lra_split_hard_reg_for()
/home/jlaw/test/gcc/gcc/lra-assigns.cc:1868
0x12e91fe lra(_IO_FILE*, int)
/home/jlaw/test/gcc/gcc/lra.cc:2518
0x1291c6b do_reload
/home/jlaw/test/gcc/gcc/ira.cc:5973
0x12920fa execute
/home/jlaw/test/gcc/gcc/ira.cc:6161
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See
[Bug rtl-optimization/115013] [15 Regression] LRA: PR114810 fix result in ICE in the RISC-V Vector
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013 Andrew Pinski changed: What|Removed |Added Target Milestone|--- |15.0 Component|c |rtl-optimization Keywords||ra Summary|LRA: PR114810 fix result in |[15 Regression] LRA: |ICE in the RISC-V Vector|PR114810 fix result in ICE ||in the RISC-V Vector
