[Bug rtl-optimization/30455] i386 generates unnecessary TEST instructions for arithmetic ops on memory

2017-04-20 Thread ubizjak at gmail dot com
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=30455

Uroš Bizjak  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #3 from Uroš Bizjak  ---
gcc-7 generates for the original testcase:

add_zf:
addl%esi, (%rdi)
movl%ecx, %eax
cmove   %edx, %eax
ret

So, fixed.

[Bug rtl-optimization/30455] i386 generates unnecessary TEST instructions for arithmetic ops on memory

2007-01-13 Thread ubizjak at gmail dot com


--- Comment #1 from ubizjak at gmail dot com  2007-01-13 23:27 ---
Addition (addl) operates in CCGOCmode and is not compatible with requested
CCZmode. Following that, test insn will be eliminated in this example:

int add_zf(int *x, int y, int a, int b)
{
 if ((*x + y)  0)
  return a;
 else
  return b;
}

add_zf:
addl(%rdi), %esi
movl%edx, %eax
cmovns  %ecx, %eax
ret

However, having assignment to *x, we enter RTL generation with:

bb 2:
  D.1972 = *x;
  temp.27 = y + D.1972;
  *x = temp.27;
  if (temp.27  0) goto L2; else goto L3;

this gets expanded into:
;; D.1972 = *x
(insn 14 12 0 (set (reg:SI 59 [ D.1972 ])
(mem:SI (reg/v/f:DI 61 [ x ]) [2 S4 A32])) -1 (nil)
(nil))

;; temp.27 = y + D.1972
(insn 15 14 0 (parallel [
(set (reg:SI 58 [ temp.27 ])
(plus:SI (reg/v:SI 62 [ y ])
(reg:SI 59 [ D.1972 ])))
(clobber (reg:CC 17 flags))
]) -1 (nil)
(nil))

;; *x = temp.27
(insn 16 15 0 (set (mem:SI (reg/v/f:DI 61 [ x ]) [2 S4 A32])
(reg:SI 58 [ temp.27 ])) -1 (nil)
(nil))

;; if (temp.27  0) goto L2;
(insn 17 16 18 (set (reg:CCGOC 17 flags)
(compare:CCGOC (reg:SI 58 [ temp.27 ])
(const_int 0 [0x0]))) -1 (nil)
(nil))

Combine pass then creates:

(insn 15 14 16 2 (parallel [
(set (reg:SI 58 [ temp.27 ])
(plus:SI (reg/v:SI 62 [ y ])
(mem:SI (reg/v/f:DI 61 [ x ]) [2 S4 A32])))
(clobber (reg:CC 17 flags))
]) 207 {*addsi_1} (insn_list:REG_DEP_TRUE 6 (insn_list:REG_DEP_TRUE 7
(nil)))
(expr_list:REG_UNUSED (reg:CC 17 flags)
(expr_list:REG_DEAD (reg/v:SI 62 [ y ])
(nil

(insn 16 15 40 2 (set (mem:SI (reg/v/f:DI 61 [ x ]) [2 S4 A32])
(reg:SI 58 [ temp.27 ])) 40 {*movsi_1} (insn_list:REG_DEP_TRUE 15
(nil))
(expr_list:REG_DEAD (reg/v/f:DI 61 [ x ])
(nil)))

(insn 40 16 41 2 (set (reg:CCGOC 17 flags)
(compare:CCGOC (reg:SI 58 [ temp.27 ])
(const_int 0 [0x0]))) 3 {*cmpsi_ccno_1} (nil)
(expr_list:REG_DEAD (reg:SI 58 [ temp.27 ])
(nil)))

Unfortunatelly, combine pass will not create a combination of insn 15 and insn
16 because reg 58 is not dead in insn 16. However, combination of insn 15, insn
16 _and_ insn 40 would produce correct pattern and something similar to your
proposed asm (cmovns instead of cmovne).


-- 

ubizjak at gmail dot com changed:

   What|Removed |Added

 CC||ubizjak at gmail dot com
   Severity|normal  |enhancement
 Status|UNCONFIRMED |NEW
  Component|target  |rtl-optimization
 Ever Confirmed|0   |1
  Known to fail||4.3.0
   Last reconfirmed|-00-00 00:00:00 |2007-01-13 23:27:24
   date||


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=30455



[Bug rtl-optimization/30455] i386 generates unnecessary TEST instructions for arithmetic ops on memory

2007-01-13 Thread ubizjak at gmail dot com


--- Comment #2 from ubizjak at gmail dot com  2007-01-13 23:43 ---
(In reply to comment #1)

 
 Combine pass then creates:
 
 (insn 15 14 16 2 (parallel [
 (set (reg:SI 58 [ temp.27 ])
 (plus:SI (reg/v:SI 62 [ y ])
 (mem:SI (reg/v/f:DI 61 [ x ]) [2 S4 A32])))
 (clobber (reg:CC 17 flags))
 ]) 207 {*addsi_1} (insn_list:REG_DEP_TRUE 6 (insn_list:REG_DEP_TRUE 7
 (nil)))
 (expr_list:REG_UNUSED (reg:CC 17 flags)
 (expr_list:REG_DEAD (reg/v:SI 62 [ y ])
 (nil
 
 (insn 16 15 40 2 (set (mem:SI (reg/v/f:DI 61 [ x ]) [2 S4 A32])
 (reg:SI 58 [ temp.27 ])) 40 {*movsi_1} (insn_list:REG_DEP_TRUE 15
 (nil))
 (expr_list:REG_DEAD (reg/v/f:DI 61 [ x ])
 (nil)))
 
 (insn 40 16 41 2 (set (reg:CCGOC 17 flags)
 (compare:CCGOC (reg:SI 58 [ temp.27 ])
 (const_int 0 [0x0]))) 3 {*cmpsi_ccno_1} (nil)
 (expr_list:REG_DEAD (reg:SI 58 [ temp.27 ])
 (nil)))

Huh, is there any reason why insn 40 does not have any insn links?? It should
link to insn 15 as it uses reg 58. This is also seen in .140r.life1 pass.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=30455