[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 Jakub Jelinek changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #25 from Jakub Jelinek --- Fixed.
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #24 from Jakub Jelinek --- Author: jakub Date: Mon Apr 8 12:36:58 2019 New Revision: 270206 URL: https://gcc.gnu.org/viewcvs?rev=270206=gcc=rev Log: PR rtl-optimization/89865 * config/i386/i386.md: Add peepholes for z = x; x ^= y; x != z. * gcc.target/i386/pr49095.c: Don't expect any RMW sequences. Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386.md trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/i386/pr49095.c
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865
--- Comment #23 from Jakub Jelinek ---
Author: jakub
Date: Mon Apr 8 12:35:22 2019
New Revision: 270205
URL: https://gcc.gnu.org/viewcvs?rev=270205=gcc=rev
Log:
PR rtl-optimization/89865
* config/i386/i386.md
(SWI12 peephole for mem {+,-,&,|,^}= x; mem != 0): Fix up operand
numbers not to clash with the additional operands[4].
(peepholes for mem {+,-,&,|,^}= x; mem != 0): New peephole2s
with extra register copy in the middle.
* gcc.target/i386/pr49095.c: Adjust number of expected RMW spots
on ia32.
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/i386/i386.md
trunk/gcc/testsuite/ChangeLog
trunk/gcc/testsuite/gcc.target/i386/pr49095.c
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #22 from Vladimir Makarov --- Author: vmakarov Date: Mon Apr 1 16:18:30 2019 New Revision: 270060 URL: https://gcc.gnu.org/viewcvs?rev=270060=gcc=rev Log: 2019-04-01 Vladimir Makarov PR rtl-optimization/89865 * ira-costs.c (process_bb_node_for_hard_reg_moves): Skip hard register if it is a part of small class. Added: trunk/gcc/ira-costs.c - copied, changed from r268424, trunk/gcc/ira-costs.c Modified: trunk/gcc/ChangeLog
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #21 from Jakub Jelinek --- Author: jakub Date: Fri Mar 29 20:51:15 2019 New Revision: 270025 URL: https://gcc.gnu.org/viewcvs?rev=270025=gcc=rev Log: PR rtl-optimization/89865 * gcc.target/i386/pr49095.c: Include in scan-assembler-times patterns the first argument register, so that occassional spills/fills are ignored. Modified: trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/i386/pr49095.c
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #20 from Vladimir Makarov --- I'll be working on this.
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 --- Comment #19 from Jakub Jelinek --- Created attachment 46059 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=46059=edit gcc9-pr89865.patch Peepholes (on top of the above testcase patch) that fix up f*minus on ia32.
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865
--- Comment #18 from Jakub Jelinek ---
The test adjustment so that it only checks what the PR85683 change really meant
to check for would be:
2019-03-29 Jakub Jelinek
PR rtl-optimization/89865
* gcc.target/i386/pr49095.c: Include in scan-assembler-times patterns
the first argument register, so that occassional spills/fills are
ignored.
--- gcc/testsuite/gcc.target/i386/pr49095.c.jj 2018-10-08 15:18:22.074105125
+0200
+++ gcc/testsuite/gcc.target/i386/pr49095.c 2019-03-29 13:11:54.941597147
+0100
@@ -73,5 +73,5 @@ G (long)
/* { dg-final { scan-assembler-not "test\[lq\]" } } */
/* The {f,h}{char,short,int,long}xor functions aren't optimized into
a RMW instruction, so need load, modify and store. FIXME eventually. */
-/* { dg-final { scan-assembler-times "\\), %" 57 { target { ia32 } } } } */
-/* { dg-final { scan-assembler-times "\\), %" 45 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-times "\\(%eax\\), %" 12 { target { ia32 } } }
} */
+/* { dg-final { scan-assembler-times "\\(%\[re\]di\\), %" 8 { target { ! ia32
} } } } */
Now, for ia32 we've regressed even there, as we emit those 8 RMWs for
{f,h}{char,short,int,long}xor,
like for m64, but also 4 RMWs for f{char,short,int,long}minus.
Will look at thos next.
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 Richard Biener changed: What|Removed |Added Priority|P3 |P1 --- Comment #17 from Richard Biener --- Should get rid of that FAIL in any way.
[Bug rtl-optimization/89865] [9 Regression] FAIL: gcc.target/i386/pr49095.c scan-assembler-times \\\\), % 45
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89865 Uroš Bizjak changed: What|Removed |Added Keywords||ra Target||x86 Status|ASSIGNED|NEW Component|target |rtl-optimization Assignee|ubizjak at gmail dot com |unassigned at gcc dot gnu.org --- Comment #16 from Uroš Bizjak --- The exposed target-related problem is fixed. Recategorizing as RA problem.
