[Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100701 Uroš Bizjak changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED|RESOLVED --- Comment #4 from Uroš Bizjak --- Fixed.
[Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100701 --- Comment #3 from CVS Commits --- The master branch has been updated by Uros Bizjak : https://gcc.gnu.org/g:a71f55c482ada2c6c31d450ac22494b547512127 commit r12-945-ga71f55c482ada2c6c31d450ac22494b547512127 Author: Uros Bizjak Date: Thu May 20 18:48:16 2021 +0200 i386: Avoid integer logic insns for 32bit and 64bit vector modes [PR100701] Integer logic instructions clobber flags, do not use them for 32bit and 64bit vector modes. 2021-05-20 Uroš Bizjak gcc/ PR target/100701 * config/i386/i386.md (isa): Remove x64_bmi. (enabled): Remove x64_bmi. * config/i386/mmx.md (mmx_andnot3): Remove general register alternative. (*andnot3): Ditto. (*mmx_3): Ditto. (*3): Ditto. gcc/testsuite/ PR target/100701 * gcc.target/i386/pr100701.c: New test.
[Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100701 Uroš Bizjak changed: What|Removed |Added Status|NEW |ASSIGNED Assignee|unassigned at gcc dot gnu.org |ubizjak at gmail dot com CC|uros at gcc dot gnu.org| --- Comment #2 from Uroš Bizjak --- (In reply to Richard Biener from comment #1) > orq %rdi, %rsi > pshuflw $0, %xmm3, %xmm0 > movq%xmm0, %rbp > and %rbx, %rbp > je .L4 > > Confirmed. Somehow the mmx_andv8qi3 doesn't clobber CC: Eh, stupid me. Let's remove integer regs from the insn patterns for now.
[Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100701
Richard Biener changed:
What|Removed |Added
Ever confirmed|0 |1
Last reconfirmed||2021-05-20
Target||x86_64-*-* i?86-*-*
Status|UNCONFIRMED |NEW
Component|rtl-optimization|target
CC||uros at gcc dot gnu.org
Target Milestone|--- |12.0
--- Comment #1 from Richard Biener ---
orq %rdi, %rsi
pshuflw $0, %xmm3, %xmm0
movq%xmm0, %rbp
and %rbx, %rbp
je .L4
Confirmed. Somehow the mmx_andv8qi3 doesn't clobber CC:
(insn 19 88 15 2 (parallel [
(set (reg:CCZ 17 flags)
(compare:CCZ (ior:DI (reg:DI 4 si [158])
(reg:DI 5 di [orig:101 i ] [101]))
(const_int 0 [0])))
(clobber (reg:DI 4 si [158]))
]) "t.c":13:6 562 {*iordi_3}
(expr_list:REG_DEAD (reg:DI 4 si [158])
(expr_list:REG_UNUSED (reg:DI 4 si [158])
(nil
(insn:TI 15 19 89 2 (set (reg:V4HI 20 xmm0 [106])
(vec_duplicate:V4HI (truncate:HI (reg:SI 23 xmm3 [162] "t.c":12:5
1459 {*vec_dupv4hi}
(expr_list:REG_DEAD (reg:SI 23 xmm3 [162])
(nil)))
(insn:TI 89 15 17 2 (set (reg/v:V8QI 6 bp [orig:95 a ] [95])
(reg:V8QI 20 xmm0 [106])) "t.c":12:5 1302 {*movv8qi_internal}
(expr_list:REG_DEAD (reg:V8QI 20 xmm0 [106])
(nil)))
(insn:TI 17 89 20 2 (set (reg/v:V8QI 6 bp [orig:95 a ] [95])
(and:V8QI (reg/v:V8QI 6 bp [orig:95 a ] [95])
(reg/v:V8QI 3 bx [orig:98 a ] [98]))) "t.c":12:5 1422
{*mmx_andv8qi3}
(nil))
(jump_insn 20 17 25 2 (set (pc)
(if_then_else (eq (reg:CCZ 17 flags)
(const_int 0 [0]))
(label_ref:DI 113)
(pc))) "t.c":13:6 822 {*jcc}
(expr_list:REG_DEAD (reg:CCZ 17 flags)
(int_list:REG_BR_PROB 7 (nil)))
