[Bug target/106959] [13 Regression] ICE in curr_insn_transform, at lra-constraints.cc:4168 (error: unable to generate reloads), or ICE in simplify_subreg, at simplify-rtx.cc:7405 since r13-2100-g5cccc

2022-12-24 Thread roger at nextmovesoftware dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106959

Roger Sayle  changed:

   What|Removed |Added

 CC||roger at nextmovesoftware dot 
com
 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #6 from Roger Sayle  ---
This should now be fixed on mainline.  Thanks HJ and Uros.

[Bug target/106959] [13 Regression] ICE in curr_insn_transform, at lra-constraints.cc:4168 (error: unable to generate reloads), or ICE in simplify_subreg, at simplify-rtx.cc:7405 since r13-2100-g5cccc

2022-12-23 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106959

--- Comment #5 from CVS Commits  ---
The master branch has been updated by Roger Sayle :

https://gcc.gnu.org/g:24a7980d0f48671ea13da18c9162a43420b5af58

commit r13-4872-g24a7980d0f48671ea13da18c9162a43420b5af58
Author: Roger Sayle 
Date:   Fri Dec 23 09:50:18 2022 +

PR target/106933: Limit TImode STV to SSA-like def-use chains on x86.

With many thanks to H.J. for doing all the hard work, this patch resolves
two P1 regressions; PR target/106933 and PR target/106959.

Although superficially similar, the i386 backend's two scalar-to-vector
(STV) passes perform their transformations in importantly different ways.
The original pass converting SImode and DImode operations to V4SImode
or V2DImode operations is "soft", allowing values to be maintained in
both integer and vector hard registers.  The newer pass converting TImode
operations to V1TImode is "hard" (all or nothing) that converts all uses
of a pseudo to vector form.  To implement this it invokes powerful ju-ju
calling SET_MODE on a reg_rtx, which due to RTL sharing, often updates
this pseudo's mode everywhere in the RTL chain.  Hence, TImode STV can only
be performed when all uses of a pseudo are convertible to V1TImode form.
To ensure this the STV passes currently use data-flow analysis to inspect
all DEFs and USEs in a chain.  This works fine for chains that are in
the usual single assignment form, but the occurrence of uninitialized
variables, or multiple assignments that split a pseudo's usage into
several independent chains (lifetimes) can lead to situations where
some but not all of a pseudo's occurrences need to be updated.  This is
safe for the SImode/DImode pass, but leads to the above bugs during
the TImode pass.

My one minor tweak to HJ's patch from comment #4 of bugzilla PR106959
is to only perform the new single_def_chain_p check for TImode STV; it
turns out that STV of SImode/DImode min/max operates safely on multiple-def
chains, and prohibiting this leads to testsuite regressions.  We don't
(yet) support V1TImode min/max, so this idiom isn't an issue during the
TImode STV pass.

For the record, the two alternate possible fixes are (i) make the TImode
STV pass "soft", by eliminating use of SET_MODE, instead using replace_rtx
with a new pseudo, or (ii) merging "chains" so that multiple DFA
chains/lifetimes are considered a single STV chain.

2022-12-23  H.J. Lu  
Roger Sayle  

gcc/ChangeLog
PR target/106933
PR target/106959
* config/i386/i386-features.cc (single_def_chain_p): New predicate
function to check that a pseudo's use-def chain is in SSA form.
(timode_scalar_to_vector_candidate_p): Check that TImode regs that
are SET_DEST or SET_SRC of an insn match/are single_def_chain_p.

gcc/testsuite/ChangeLog
PR target/106933
PR target/106959
* gcc.target/i386/pr106933-1.c: New test case.
* gcc.target/i386/pr106933-2.c: Likewise.
* gcc.target/i386/pr106959-1.c: Likewise.
* gcc.target/i386/pr106959-2.c: Likewise.
* gcc.target/i386/pr106959-3.c: Likewise.

[Bug target/106959] [13 Regression] ICE in curr_insn_transform, at lra-constraints.cc:4168 (error: unable to generate reloads), or ICE in simplify_subreg, at simplify-rtx.cc:7405 since r13-2100-g5cccc

2022-10-20 Thread hjl.tools at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106959

--- Comment #4 from H.J. Lu  ---
Created attachment 53738
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53738&action=edit
A patch

[Bug target/106959] [13 Regression] ICE in curr_insn_transform, at lra-constraints.cc:4168 (error: unable to generate reloads), or ICE in simplify_subreg, at simplify-rtx.cc:7405 since r13-2100-g5cccc

2022-10-20 Thread asolokha at gmx dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106959

--- Comment #3 from Arseny Solokha  ---
Here's a shorter testcase that AFAICT doesn't rely on UB:

unsigned __int128 m;
int n;

__attribute__ ((simd)) void
foo (int x)
{
  x = n ? n : (short int) x;
  if (x)
m /= 2;
}

gcc 13.0.0 20221016 snapshot ICEs on that w/ just -O2 -fpeel-loops (and,
optionally, --param max-combine-insns=2, as before).

[Bug target/106959] [13 Regression] ICE in curr_insn_transform, at lra-constraints.cc:4168 (error: unable to generate reloads), or ICE in simplify_subreg, at simplify-rtx.cc:7405 since r13-2100-g5cccc

2022-10-18 Thread rguenth at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106959

Richard Biener  changed:

   What|Removed |Added

   Priority|P3  |P1

[Bug target/106959] [13 Regression] ICE in curr_insn_transform, at lra-constraints.cc:4168 (error: unable to generate reloads), or ICE in simplify_subreg, at simplify-rtx.cc:7405 since r13-2100-g5cccc

2022-09-20 Thread marxin at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106959

Martin Liška  changed:

   What|Removed |Added

   Keywords|needs-bisection |
   Last reconfirmed||2022-09-20
 Status|UNCONFIRMED |NEW
 Ever confirmed|0   |1
 CC||marxin at gcc dot gnu.org
Summary|[13 Regression] ICE in  |[13 Regression] ICE in
   |curr_insn_transform, at |curr_insn_transform, at
   |lra-constraints.cc:4168 |lra-constraints.cc:4168
   |(error: unable to generate  |(error: unable to generate
   |reloads), or ICE in |reloads), or ICE in
   |simplify_subreg, at |simplify_subreg, at
   |simplify-rtx.cc:7405|simplify-rtx.cc:7405 since
   ||r13-2100-g524c06610d2f

--- Comment #2 from Martin Liška  ---
Started with r13-2100-g524c06610d2f.