[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Jeffrey A. Law changed: What|Removed |Added Resolution|--- |FIXED Status|ASSIGNED|RESOLVED --- Comment #3 from Jeffrey A. Law --- Fixed on the trunk.
[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 --- Comment #2 from CVS Commits --- The master branch has been updated by Jeff Law : https://gcc.gnu.org/g:a647198fcf7463a42c8e035a429200e7998735dc commit r13-7198-ga647198fcf7463a42c8e035a429200e7998735dc Author: Jeff Law Date: Sun Apr 16 09:55:32 2023 -0600 [committed] [PR target/109508] Adjust conditional move expansion for SFB Recently the conditional move expander's predicates were loosened for the benefit of the THEAD processors. In particular one operand that was previously "register_operand" is now "reg_or_0_operand". That's fine for THEAD, but breaks for SFB which requires a register for that operand. This results in an ICE when compiling the testcase an SFB target such as the sifive s76. This change adjusts the expansion code slightly to copy the value into a register for SFB. Bootstrapped and regression tested (c,c++,fortran only) with a toolchain configured to enable SFB by default. PR target/109508 gcc/ * config/riscv/riscv.cc (riscv_expand_conditional_move): For TARGET_SFB_ALU, force the true arm into a register. gcc/testsuite * gcc.target/riscv/pr109508.c: New test.
[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Richard Biener changed: What|Removed |Added Status|NEW |ASSIGNED
[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Richard Biener changed: What|Removed |Added Target Milestone|--- |13.0
[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Jeffrey A. Law changed: What|Removed |Added Assignee|unassigned at gcc dot gnu.org |law at gcc dot gnu.org Priority|P3 |P4 --- Comment #1 from Jeffrey A. Law --- Trivial issue in the riscv backend. We just need to fix the operand on the movXXcc pattern.
[Bug target/109508] [13 Regression] ICE: in extract_insn, at recog.cc:2791 with -mcpu=sifive-s76 on riscv64
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109508 Jeffrey A. Law changed: What|Removed |Added Ever confirmed|0 |1 Last reconfirmed||2023-04-14 Status|UNCONFIRMED |NEW
