[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748

Kito Cheng  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|UNCONFIRMED |RESOLVED

--- Comment #4 from Kito Cheng  ---
Should be resolved at trunk.

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748

--- Comment #3 from CVS Commits  ---
The master branch has been updated by Kito Cheng :

https://gcc.gnu.org/g:8421f279e9eb00a2342ee3630dcdaf735b734fe8

commit r14-538-g8421f279e9eb00a2342ee3630dcdaf735b734fe8
Author: Juzhe-Zhong 
Date:   Fri May 5 22:12:39 2023 +0800

RISC-V: Fix incorrect demand info merge in local vsetvli optimization
[PR109748]

This patch is fixing my recent optimization patch:
   
https://github.com/gcc-mirror/gcc/commit/d51f2456ee51bd59a79b4725ca0e488c25260bbf

In that patch, the new_info = parse_insn (i) is not correct.
Since consider the following case:

vsetvli a5,a4, e8,m1
..
vsetvli zero,a5, e32, m4
vle8.v
vmacc.vv
...

Since we have backward demand fusion in Phase 1, so the real demand of
"vle8.v" is e32, m4.
However, if we use parse_insn (vle8.v) = e8, m1 which is not correct.

So this patch we change new_info = new_info.parse_insn (i)
into:

vector_insn_info new_info = m_vector_manager->vector_insn_infos[i->uid ()];

So that, we can correctly optimize codes into:

vsetvli a5,a4, e32, m4
..
.. (vsetvli zero,a5, e32, m4 is removed)
vle8.v
vmacc.vv

Since m_vector_manager->vector_insn_infos is the member variable of
pass_vsetvl class.
We remove static void function "local_eliminate_vsetvl_insn", and make it
as the member function
of pass_vsetvl class.

PR target/109748

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn):
Remove it.
(pass_vsetvl::local_eliminate_vsetvl_insn): New function.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr109748.c: New test.

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread pan2.li at intel dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748

--- Comment #2 from Li Pan  ---
No, should be introduced by one optimization of Juzhe in GCC 14. Juzhe is
working on fixing this, just open a bug on behalf of Juzhe for tracking.

[Bug target/109748] RISC-V: Mis code gen for the RVV intrinsic VSETVL

2023-05-05 Thread kito at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109748

--- Comment #1 from Kito Cheng  ---
Is this also happened in GCC 13 branch?