[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977 Jakub Jelinek changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #7 from Jakub Jelinek --- Fixed.
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977 --- Comment #6 from CVS Commits --- The master branch has been updated by Jakub Jelinek : https://gcc.gnu.org/g:a6a43a3b763816fec7c4eec6ae7be5b263dff340 commit r14-5840-ga6a43a3b763816fec7c4eec6ae7be5b263dff340 Author: Jakub Jelinek Date: Sat Nov 25 10:30:39 2023 +0100 aarch64: Fix up aarch64_simd_stp [PR109977] The aarch64_simd_stp pattern uses w constraint in one alternative and r in another, but for the latter incorrectly uses iterator in %1 which expands to %d1 for V2DF and %s1 for V2SF and V4SF (this one not relevant to the pattern) and %w1 for others, so it ICEs if the alternative is selected during final. Compared to this, macro has the same values for all modes but uses w for V2DF and V2SF. 2023-11-24 Andrew Pinski Jakub Jelinek PR target/109977 * config/aarch64/aarch64-simd.md (aarch64_simd_stp): Use rather than % for alternative with r constraint on input operand. * gcc.dg/pr109977.c: New test.
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977 --- Comment #5 from Sam James --- If needed, you can email me an SSH key for a Neoverse-N1 (fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp ssbs) which should be fast.
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Jakub Jelinek changed:
What|Removed |Added
CC||jakub at gcc dot gnu.org
--- Comment #4 from Jakub Jelinek ---
I agree with the analysis and
2023-11-24 Andrew Pinski
Jakub Jelinek
* config/aarch64/aarch64-simd.md (aarch64_simd_stp): Use
rather than % for alternative with r constraint on input operand.
* gcc.dg/pr109977.c: New test.
--- gcc/config/aarch64/aarch64-simd.md.jj 2023-11-22 22:55:20.577075762
+0100
+++ gcc/config/aarch64/aarch64-simd.md 2023-11-24 12:51:22.855215700 +0100
@@ -269,7 +269,7 @@ (define_insn "aarch64_simd_stp"
"TARGET_SIMD"
{@ [ cons: =0 , 1 ; attrs: type]
[ Umn , w ; neon_stp ] stp\t%1, %1,
%y0
- [ Umn , r ; store_ ] stp\t%1, %1, %y0
+ [ Umn , r ; store_ ] stp\t%1, %1,
%y0
}
)
--- gcc/testsuite/gcc.dg/pr109977.c.jj 2023-11-24 12:51:04.551473591 +0100
+++ gcc/testsuite/gcc.dg/pr109977.c 2023-11-24 12:50:44.158760916 +0100
@@ -0,0 +1,16 @@
+/* PR target/109977 */
+/* { dg-do compile } */
+/* { dg-options "-Og" } */
+
+typedef double __attribute__((__vector_size__ (8))) V;
+typedef double __attribute__((__vector_size__ (16))) W;
+V v;
+int i;
+extern void bar (void *);
+
+void
+foo (void)
+{
+ W w = __builtin_shufflevector (v, (W) { }, 0, 0);
+ bar ();
+}
fixes it (though it will take me a while to find where to bootstrap/regtest
this).
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977 Richard Biener changed: What|Removed |Added Priority|P3 |P1
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977 Andrew Pinski changed: What|Removed |Added CC||slyfox at gcc dot gnu.org --- Comment #3 from Andrew Pinski --- *** Bug 110880 has been marked as a duplicate of this bug. ***
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977 --- Comment #2 from Andrew Pinski --- Introduced by r14-215-g85279b0bddc1c5 .
[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977
Andrew Pinski changed:
What|Removed |Added
Target Milestone|--- |14.0
Host|x86_64-pc-linux-gnu |
Last reconfirmed||2023-05-26
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
--- Comment #1 from Andrew Pinski ---
(insn 12 11 13 (set (mem/c:V2DF (plus:DI (reg/f:DI 31 sp)
(const_int 16 [0x10])) [1 w+0 S16 A128])
(vec_duplicate:V2DF (reg:DF 0 x0 [orig:95 v ] [95])))
"/app/example.cpp":12:5 1392 {aarch64_simd_stpv2df}
(expr_list:REG_DEAD (reg:DF 0 x0 [orig:95 v ] [95])
(nil)))
(define_insn "aarch64_simd_stp"
[(set (match_operand:VP_2E 0 "aarch64_mem_pair_lanes_operand" "=Umn,Umn")
(vec_duplicate:VP_2E (match_operand: 1 "register_operand"
"w,r")))]
"TARGET_SIMD"
"@
stp\\t%1, %1, %y0
stp\\t%1, %1, %y0"
[(set_attr "type" "neon_stp, store_")]
)
;; For scalar usage of vector/FP registers, widening
(define_mode_attr vw [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V2SF "s") (V4SF "s")
(V2DF "d")])
Most likely should be using vwcore instead:
;; Corresponding core element mode for each vector mode. This is a
;; variation on mapping FP modes to GP regs.
(define_mode_attr vwcore [(V8QI "w") (V16QI "w")
(V4HI "w") (V8HI "w")
(V2SI "w") (V4SI "w")
(DI "x") (V2DI "x")
(V4HF "w") (V8HF "w")
(V4BF "w") (V8BF "w")
(V2SF "w") (V4SF "w")
(V2DF "x")
(VNx16QI "w") (VNx8QI "w") (VNx4QI "w") (VNx2QI "w")
(VNx8HI "w") (VNx4HI "w") (VNx2HI "w")
(VNx8HF "w") (VNx4HF "w") (VNx2HF "w")
(VNx8BF "w") (VNx4BF "w") (VNx2BF "w")
(VNx4SI "w") (VNx2SI "w")
(VNx4SF "w") (VNx2SF "w")
(VNx2DI "x")
(VNx2DF "x")])
