[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-11-12 Thread ubizjak at gmail dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #9 from Uroš Bizjak  ---
(In reply to Andrew Pinski from comment #8)
> I need some code generation help for gcc.target/i386/pr110790-2.c, I have a
> patch where we now generate:
> ```
> movq(%rdi,%rax,8), %rax
> shrq%cl, %rax
> andl$1, %eax
> ```
> 
> instead of previously:
> ```
> movq(%rdi,%rax,8), %rax
> btq %rsi, %rax
> setc%al
> movzbl  %al, %eax
> ```
> 
> I suspect the sequence that contains shrq/and is better but I am 100% sure.
> We still get btq when used with a conditional too.

The new sequence is better. It does not create a partial reg write (setc needs
a clearing XOR in fron of CC-setting instruction).

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-11-12 Thread pinskia at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #8 from Andrew Pinski  ---
I need some code generation help for gcc.target/i386/pr110790-2.c, I have a
patch where we now generate:
```
movq(%rdi,%rax,8), %rax
shrq%cl, %rax
andl$1, %eax
```

instead of previously:
```
movq(%rdi,%rax,8), %rax
btq %rsi, %rax
setc%al
movzbl  %al, %eax
```

I suspect the sequence that contains shrq/and is better but I am 100% sure. We
still get btq when used with a conditional too.

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-29 Thread slyfox at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #7 from Sergei Trofimovich  ---
The new change did not break `grep`, `gmp` and `mpfr` on x86_64-linux and
i686-linux. Success!

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-29 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #6 from CVS Commits  ---
The master branch has been updated by Roger Sayle :

https://gcc.gnu.org/g:e68a31549d9827030391d837951be96a5f95f291

commit r14-2866-ge68a31549d9827030391d837951be96a5f95f291
Author: Roger Sayle 
Date:   Sat Jul 29 17:07:58 2023 +0100

[Committed] Use QImode for offsets in zero_extract/sign_extract in i386.md

As suggested by Uros, this patch changes the ZERO_EXTRACTs and
SIGN_EXTRACTs
in i386.md to consistently use QImode for bit offsets (i.e. third and
fourth
operands), matching the use of QImode for bit counts in shifts and rotates.

This iteration also corrects the "ne:QI" vs "eq:QI" mistake in the previous
version, which was responsible for PR 110787 and PR 110790 and so was
rapidly reverted last weekend.  New test cases have been added to check
the correct behaviour.

2023-07-29  Roger Sayle  

gcc/ChangeLog
PR target/110790
* config/i386/i386.md (extv): Use QImode for offsets.
(extzv): Likewise.
(insv): Likewise.
(*testqi_ext_3): Likewise.
(*btr_2): Likewise.
(define_split): Likewise.
(*btsq_imm): Likewise.
(*btrq_imm): Likewise.
(*btcq_imm): Likewise.
(define_peephole2 x3): Likewise.
(*bt): Likewise
(*bt_mask): New define_insn_and_split.
(*jcc_bt): Use QImode for offsets.
(*jcc_bt_1): Delete obsolete pattern.
(*jcc_bt_mask): Use QImode offsets.
(*jcc_bt_mask_1): Likewise.
(define_split): Likewise.
(*bt_setcqi): Likewise.
(*bt_setncqi): Likewise.
(*bt_setnc): Likewise.
(*bt_setncqi_2): Likewise.
(*bt_setc_mask): New define_insn_and_split.
(bmi2_bzhi_3): Use QImode offsets.
(*bmi2_bzhi_3): Likewise.
(*bmi2_bzhi_3_1): Likewise.
(*bmi2_bzhi_3_1_ccz): Likewise.
(@tbm_bextri_): Likewise.

gcc/testsuite/ChangeLog
PR target/110790
* gcc.target/i386/pr110790-1.c: New test case.
* gcc.target/i386/pr110790-2.c: Likewise.

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-25 Thread roger at nextmovesoftware dot com via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #5 from Roger Sayle  ---
I'll add this testcase to the testsuite, when I apply a corrected version of my
QImode offset patch to mainline.  On the bright side, we'll be generating more
efficient code for gmp's refmpn_tstbit by using the x86's bt instruction (it
just needs to use setc not setnc in this case).

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-24 Thread rguenth at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

Richard Biener  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
   Target Milestone|--- |14.0
   Keywords||wrong-code
 Target||i?86-*-*
 Resolution|--- |FIXED

--- Comment #4 from Richard Biener  ---
Fixed.

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-24 Thread slyfox at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #3 from Sergei Trofimovich  ---
The change fixed `gmp` and `mpfr` test suites on `i686-linux` for me. And also
a `grep` testsuite on `x86_64-linux`. Thank you!

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-24 Thread cvs-commit at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

--- Comment #2 from CVS Commits  ---
The master branch has been updated by Roger Sayle :

https://gcc.gnu.org/g:9f66753ef48f37729a88735ae1a2bf2d2558e69f

commit r14-2743-g9f66753ef48f37729a88735ae1a2bf2d2558e69f
Author: Roger Sayle 
Date:   Mon Jul 24 12:34:23 2023 +0100

[Committed] PR target/110787: Revert QImode offsets in {zero,sign}_extract.

My recent patch to use QImode for bit offsets in ZERO_EXTRACTs and
SIGN_EXTRACTs in the i386 backend shouldn't have resulted in any change
behaviour, but as reported by Rainer it produces a bootstrap failure in
gm2.  This reverts the problematic patch whilst we investigate the
underlying cause.

Committed as obvious.

2023-07-23  Roger Sayle  

gcc/ChangeLog
PR target/110787
PR target/110790
Revert patch.
* config/i386/i386.md (extv): Use QImode for offsets.
(extzv): Likewise.
(insv): Likewise.
(*testqi_ext_3): Likewise.
(*btr_2): Likewise.
(define_split): Likewise.
(*btsq_imm): Likewise.
(*btrq_imm): Likewise.
(*btcq_imm): Likewise.
(define_peephole2 x3): Likewise.
(*bt): Likewise
(*bt_mask): New define_insn_and_split.
(*jcc_bt): Use QImode for offsets.
(*jcc_bt_1): Delete obsolete pattern.
(*jcc_bt_mask): Use QImode offsets.
(*jcc_bt_mask_1): Likewise.
(define_split): Likewise.
(*bt_setcqi): Likewise.
(*bt_setncqi): Likewise.
(*bt_setnc): Likewise.
(*bt_setncqi_2): Likewise.
(*bt_setc_mask): New define_insn_and_split.
(bmi2_bzhi_3): Use QImode offsets.
(*bmi2_bzhi_3): Likewise.
(*bmi2_bzhi_3_1): Likewise.
(*bmi2_bzhi_3_1_ccz): Likewise.
(@tbm_bextri_): Likewise.

[Bug target/110790] [14 Regression] gcc -m32 generates invalid bit test code on gmp-6.2.1

2023-07-24 Thread slyfox at gcc dot gnu.org via Gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110790

Sergei Trofimovich  changed:

   What|Removed |Added

 CC||roger at nextmovesoftware dot 
com

--- Comment #1 from Sergei Trofimovich  ---
I suspect it's a r14-2728-g59c38ddfe052a4 (the only change I see in recent
commits that have any relevance here). I did not try to revert locally.