https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111450
--- Comment #1 from CVS Commits ---
The master branch has been updated by Li Xu :
https://gcc.gnu.org/g:47065ff360292c683670efb96df4b61f57dc1d9a
commit r14-4190-g47065ff360292c683670efb96df4b61f57dc1d9a
Author: xuli
Date: Thu Sep 21 03:04:56 2023 +
RISC-V: Optimized for strided load/store with stride == element
width[PR111450]
When stride == element width, vlsse should be optimized into vle.v.
vsse should be optimized into vse.v.
PR target/111450
gcc/ChangeLog:
* config/riscv/constraints.md (c01): const_int 1.
(c02): const_int 2.
(c04): const_int 4.
(c08): const_int 8.
* config/riscv/predicates.md (vector_eew8_stride_operand): New
predicate for stride operand.
(vector_eew16_stride_operand): Ditto.
(vector_eew32_stride_operand): Ditto.
(vector_eew64_stride_operand): Ditto.
* config/riscv/vector-iterators.md: New iterator for stride
operand.
* config/riscv/vector.md: Add stride = element width constraint.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr111450.c: New test.
