[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 Jeremy Bennett changed: What|Removed |Added Resolution|--- |FIXED Status|UNCONFIRMED |RESOLVED --- Comment #7 from Jeremy Bennett --- I can confirm this is resolved, and also that SPEC CPU 2017 627.cam4_s compiles successfully. Thanks for the patch. Marking as resolved.
[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 --- Comment #6 from CVS Commits --- The master branch has been updated by Joern Rennecke : https://gcc.gnu.org/g:f416a3fdbee32ae12b055b8e3e4ee11c3df7c117 commit r14-4353-gf416a3fdbee32ae12b055b8e3e4ee11c3df7c117 Author: Joern Rennecke Date: Sun Oct 1 06:13:37 2023 +0100 Make riscv_vector::legitimize_move adjust SRC in the caller. 2023-09-29 Joern Rennecke Juzhe-Zhong PR target/111566 gcc/ * config/riscv/riscv-protos.h (riscv_vector::legitimize_move): Change second parameter to rtx *. * config/riscv/riscv-v.cc (risv_vector::legitimize_move): Likewise. * config/riscv/vector.md: Changed callers of riscv_vector::legitimize_move. (*mov_mem_to_mem): Remove. gcc/testsuite/ * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.1 * gcc.target/riscv/rvv/autovec/vls/mov-2.c: Removed. * gcc.target/riscv/rvv/autovec/vls/mov-4.c: Removed. * gcc.target/riscv/rvv/autovec/vls/mov-6.c: Removed. * gcc.target/riscv/rvv/fortran/pr111566.f90: New test. Co-Authored-By: Juzhe-Zhong
[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 --- Comment #5 from Jorn Wolfgang Rennecke --- I had a look at riscv_legitimize_move. It doesn't seem to suffer from quite the same problem as legitimize_move does, but it could if another problem was fixed: riscv_legitimize_move changes the rtl it's passed. That can lead to trouble if this is shared rtl.
[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 --- Comment #4 from Jorn Wolfgang Rennecke --- Also, the GET_MODE_BITSIZE (mode).to_constant () <= MAX_BITS_PER_WORD in the *mov_mem_to_mem splitter can generate unaligned accesses, yet it is not guarded by a check that the target supports them.
[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 --- Comment #3 from Jorn Wolfgang Rennecke --- riscv-v.cc:legitimize_move has: if (MEM_P (dest) && !REG_P (src)) src = force_reg (mode, src); return false; since src is passed by value, this is pointless. The caller still had src as a MEM.
[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566
Jorn Wolfgang Rennecke changed:
What|Removed |Added
CC||amylaar at gcc dot gnu.org
--- Comment #2 from Jorn Wolfgang Rennecke ---
This also causes trouble with my cpymem patch.
With the *movv8si_mem_to_mem pattern, ira.cc:combine_and_move_insns
will eagerly transform
(insn 1606 1603 1608 77 (set (reg/f:SI 1187)
(plus:SI (reg/f:SI 65 frame)
(const_int -1248 [0xfb20])))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 4 {*addsi3}
(nil))
(insn 1608 1606 1609 77 (set (reg:V8SI 1189)
(mem/u/c:V8SI (reg/f:SI 5064) [0 S32 A128]))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 1151 {*movv8si}
(expr_list:REG_DEAD (reg/f:SI 5064)
(expr_list:REG_EQUAL (mem/u/c:V8SI (const:SI (plus:SI (symbol_ref:SI
("*.LANCHOR0") [flags 0x182])
(const_int 64 [0x40]))) [0 S32 A128])
(nil
(insn 1609 1608 12961 77 (set (mem/v/c:V8SI (reg/f:SI 1187) [1 S32 A128])
(reg:V8SI 1189))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 1151 {*movv8si}
(expr_list:REG_DEAD (reg:V8SI 1189)
(expr_list:REG_DEAD (reg/f:SI 1187)
(nil
into
(insn 1608 1603 16000 77 (set (reg:V8SI 1189)
(mem/u/c:V8SI (reg/f:SI 5064) [0 S32 A128]))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 1151 {*movv8si}
(expr_list:REG_EQUIV (mem/u/c:V8SI (const:SI (plus:SI (symbol_ref:SI
("*.LANCHOR0") [flags 0x182])
(const_int 64 [0x40]))) [0 S32 A128])
(expr_list:REG_DEAD (reg/f:SI 5064)
(nil
(insn 16000 1608 1609 77 (set (reg/f:SI 1187)
(plus:SI (reg/f:SI 65 frame)
(const_int -1248 [0xfb20])))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 4 {*addsi3}
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 65 frame)
(const_int -1248 [0xfb20]))
(nil)))
(insn 1609 16000 12961 77 (set (mem/v/c:V8SI (reg/f:SI 1187) [1 S32 A128])
(mem/u/c:V8SI (reg/f:SI 5064) [0 S32 A128]))
"/home/amylaar/embecosm/fsf-cme3/gcc/gcc/testsuite/c-c++-common/torture/complex-sign-add.c":44:0
discrim 126 -1
(expr_list:REG_DEAD (reg:V8SI 1189)
(expr_list:REG_DEAD (reg/f:SI 1187)
(nil
during compilation of check_add_long_double.
When a pattern with a mandatory split is recognized, you must make sure it can
be split. If the pattern ceases to be valid at some point during the
compilation, you must make sure it can be split or otherwise transformed
before another attempt to recognize it is made.
[Bug target/111566] RISC-V Vector Fortran: ICE in final_scan_insn_1 (final RTL pass)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111566 Andrew Pinski changed: What|Removed |Added Component|middle-end |target Keywords||ice-on-valid-code --- Comment #1 from Andrew Pinski --- fmax-stack-var-size just changes if (the VLA) dc, ch, ci, and cj are allocated on the stack or in the heap.
