[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #14 from Jeffrey A. Law --- *** Bug 112530 has been marked as a duplicate of this bug. ***
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Andrew Stubbs changed: What|Removed |Added Status|ASSIGNED|RESOLVED Resolution|--- |FIXED --- Comment #13 from Andrew Stubbs --- This should be fixed now.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #12 from CVS Commits --- The master branch has been updated by Andrew Stubbs : https://gcc.gnu.org/g:948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3 commit r14-5453-g948b8b6e0e50958ecf56d4d9fb7ac16f245d9cc3 Author: Andrew Stubbs Date: Tue Nov 14 16:07:37 2023 + Fix ICE generating uniform vector masks Most targets have an "and" instructions for their vector mask size, but RISC-V only has DImode "and". Fixed by allowing wider instruction modes. gcc/ChangeLog: PR target/112481 * expr.cc (store_constructor): Use OPTAB_WIDEN for mask adjustment.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Jeffrey A. Law changed: What|Removed |Added CC||law at gcc dot gnu.org --- Comment #11 from Jeffrey A. Law --- It's sensible, but what's the value in having a SImode variant on rv64 when we have WORD_REGISTER_OPERATIONS defined? I think the right fix here is to remove that pattern (and potentially others like it).
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Robin Dapp changed: What|Removed |Added CC||palmer at dabbelt dot com --- Comment #10 from Robin Dapp --- Palmer last touched this for the initial port: ;; For RV64, we don't expose the SImode operations to the rtl expanders, ;; but SImode versions exist for combine. (define_expand "and3" ... (define_insn "*si3_internal" [(set (match_operand:SI 0 "register_operand" "=r,r") (any_bitwise:SI (match_operand:SI 1 "register_operand" "%r,r") (match_operand:SI 2 "arith_operand"" r,I")))] "TARGET_64BIT" "%i2\t%0,%1,%2"
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #9 from rguenther at suse dot de --- On Tue, 14 Nov 2023, ams at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 > > --- Comment #7 from Andrew Stubbs --- > Simply changing to OPTAB_WIDEN solves the ICE, but I don't know if it does so > in a sensible way, for RISC V. > > @@ -7489,7 +7489,7 @@ store_constructor (tree exp, rtx target, int cleared, > poly_int64 size, > if (maybe_ne (GET_MODE_PRECISION (mode), nunits)) > tmp = expand_binop (mode, and_optab, tmp, > GEN_INT ((1 << nunits) - 1), target, > - true, OPTAB_DIRECT); > + true, OPTAB_WIDEN); > if (tmp != target) > emit_move_insn (target, tmp); > break; > > Here are the instructions it generates: > > (set (reg:DI 165) > (and:DI (subreg:DI (reg:SI 164) 0) > (const_int 1 [0x1]))) > (set (reg:SI 154) > (subreg:SI (reg:DI 165) 0)) > > Should I use that patch? I think it's harmless on targets where OPTAB_DIRECT > would work. I think that's sensible.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #8 from JuzheZhong --- I am not familiar with scalar stuff of RISC-V. CCing kito, Robin and Jeff to confirm this issue.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #7 from Andrew Stubbs --- Simply changing to OPTAB_WIDEN solves the ICE, but I don't know if it does so in a sensible way, for RISC V. @@ -7489,7 +7489,7 @@ store_constructor (tree exp, rtx target, int cleared, poly_int64 size, if (maybe_ne (GET_MODE_PRECISION (mode), nunits)) tmp = expand_binop (mode, and_optab, tmp, GEN_INT ((1 << nunits) - 1), target, - true, OPTAB_DIRECT); + true, OPTAB_WIDEN); if (tmp != target) emit_move_insn (target, tmp); break; Here are the instructions it generates: (set (reg:DI 165) (and:DI (subreg:DI (reg:SI 164) 0) (const_int 1 [0x1]))) (set (reg:SI 154) (subreg:SI (reg:DI 165) 0)) Should I use that patch? I think it's harmless on targets where OPTAB_DIRECT would work.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #6 from rguenther at suse dot de --- On Mon, 13 Nov 2023, ams at gcc dot gnu.org wrote: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 > > Andrew Stubbs changed: > >What|Removed |Added > > Status|UNCONFIRMED |ASSIGNED >Last reconfirmed||2023-11-13 > Ever confirmed|0 |1 >Assignee|unassigned at gcc dot gnu.org |ams at gcc dot gnu.org > > --- Comment #4 from Andrew Stubbs --- > It fails because optab_handler fails to find an instruction for "and_optab" in > SImode. I didn't consider handling that case; seems so unlikely. It sounds odd at least - I don't remember us having fallback for this. Ah, well, maybe OPTAB_WIDEN - guess that might be a hint how to fix it?
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Patrick O'Neill changed: What|Removed |Added CC||juzhe.zhong at rivai dot ai, ||patrick at rivosinc dot com --- Comment #5 from Patrick O'Neill --- +cc Juzhe to make sure it shouldn't be fixed by defining a new insn in the risc-v backend.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Andrew Stubbs changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Last reconfirmed||2023-11-13 Ever confirmed|0 |1 Assignee|unassigned at gcc dot gnu.org |ams at gcc dot gnu.org --- Comment #4 from Andrew Stubbs --- It fails because optab_handler fails to find an instruction for "and_optab" in SImode. I didn't consider handling that case; seems so unlikely. I guess architectures that can't "and" masks don't get to have safe masks? ... I'll work on a fix.
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Richard Biener changed: What|Removed |Added CC||rguenth at gcc dot gnu.org Priority|P3 |P1 Target||riscv
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #3 from Patrick O'Neill --- Initial bisection was correct: r14-5319-ga5922427c29
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #2 from Patrick O'Neill --- Sorry - got overzealous and mixed up my terminals. Still bisecting. Good: 8da8b9225762126ca41b12243d6531cd41a831b3 Bad: a5922427c29fad177251d89cc946d1c5bfc135eb
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 --- Comment #1 from Patrick O'Neill --- First bad commit: r14-5319-ga5922427c29
[Bug target/112481] [14 Regression] RISCV: ICE: Segmentation fault when compiling pr110817-3.c
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112481 Andrew Pinski changed: What|Removed |Added Keywords||ice-on-valid-code Target Milestone|--- |14.0
