[Bug target/112535] [14 regression] RISC-V ICE: error: unable to find a register to spill during RTL pass: reload

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112535

Richard Biener  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED
   Target Milestone|--- |14.0

--- Comment #2 from Richard Biener  ---
Fixed I suppose.

[Bug target/112535] [14 regression] RISC-V ICE: error: unable to find a register to spill during RTL pass: reload

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112535

--- Comment #1 from CVS Commits  ---
The master branch has been updated by Pan Li :

https://gcc.gnu.org/g:d85161a73b9bdd382e62ca1ba3f9f962971a9695

commit r14-5479-gd85161a73b9bdd382e62ca1ba3f9f962971a9695
Author: Juzhe-Zhong 
Date:   Wed Nov 15 15:15:08 2023 +0800

RISC-V: Disallow RVV mode address for any load/store[PR112535]

This patch is quite obvious patch which disallow for load/store address
register
with RVV mode.

PR target/112535

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimate_address_p): Disallow RVV
modes base address.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/pr112535.c: New test.