[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #8 from bernds at gcc dot gnu dot org 2010-06-11 22:36 --- Fixed. -- bernds at gcc dot gnu dot org changed: What|Removed |Added Status|NEW |RESOLVED Resolution||FIXED http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #7 from bernds at gcc dot gnu dot org 2010-04-29 21:37 --- Subject: Bug 42895 Author: bernds Date: Thu Apr 29 21:37:01 2010 New Revision: 158911 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=158911 Log: PR target/42895 * doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from ORDER_REGS_FOR_LOCAL_ALLOC. All instances of this macro changed. (HONOR_REG_ALLOC_ORDER): Describe new macro. * ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined. * ira-color.c (assign_hard_reg): Take prologue/epilogue costs into account only if HONOR_REG_ALLOC_ORDER is not defined. * config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define. * system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison. Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm.h trunk/gcc/config/avr/avr.h trunk/gcc/config/i386/i386.h trunk/gcc/config/mips/mips.h trunk/gcc/config/picochip/picochip.h trunk/gcc/config/sparc/sparc.h trunk/gcc/config/xtensa/xtensa.h trunk/gcc/doc/tm.texi trunk/gcc/ira-color.c trunk/gcc/ira.c trunk/gcc/system.h -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #6 from carrot at google dot com 2010-01-29 22:47 --- I tried to change the register order in REG_ALLOC_ORDER, moved ip and lr after r4/r5/r6/r7, but I still got the same result. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #5 from steven at gcc dot gnu dot org 2010-01-29 19:49 --- This isn't confusing at all. ORDER_REGS_FOR_LOCAL_ALLOC is unused. All targets that define it should be fixed. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #4 from carrot at google dot com 2010-01-29 19:42 ---
(In reply to comment #3)
> See arm.c:#define REG_ALLOC_ORDER. Comment before it says: " It is good to use
> ip since no saving is required (though calls clobber it) and it never contains
> function parameters. It is quite good to use lr since other calls may clobber
> it anyway."
>
> So in REG_ALLOC_ORDER, ip (reg 12) and lr (reg 14) come before before r4-r7:
>
> #define REG_ALLOC_ORDER \
> { \
> 3, 2, 1, 0, 12, 14, 4, 5, \
> 6, 7, 8, 10, 9, 11, 13, 15, \
> 16, 17, 18, 19, 20, 21, 22, 23, \
> 27, 28, 29, 30, 31, 32, 33, 34, \
> 35, 36, 37, 38, 39, 40, 41, 42, \
> 43, 44, 45, 46, 47, 48, 49, 50, \
> 51, 52, 53, 54, 55, 56, 57, 58, \
> 59, 60, 61, 62, \
> 24, 25, 26, \
>
> So the register allocator faithfully does what the IBTK has asked it to :-)
>
When I set the option -march=armv5te, gcc can generate the expected result, use
r6 and r7 instead of ip. Then I noticed the function
arm_order_regs_for_local_alloc which over writes the default REG_ALLOC_ORDER
with
/* Order of allocation of core registers for Thumb: this allocation is
written over the corresponding initial entries of the array
initialized with REG_ALLOC_ORDER. We allocate all low registers
first. Saving and restoring a low register is usually cheaper than
using a call-clobbered high register. */
static const int thumb_core_reg_alloc_order[] =
{
3, 2, 1, 0, 4, 5, 6, 7,
14, 12, 8, 9, 10, 11, 13, 15
};
But the confusion part is:
1. It rewrites the order when the target is TARGET_THUMB, it should also impact
THUMB2.
2. When I set a breakpoint to arm_order_regs_for_local_alloc and try to find
when the order is changed, the breakpoint is never triggered, even with option
-march=armv5te.
--
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #3 from steven at gcc dot gnu dot org 2010-01-29 08:42 ---
See arm.c:#define REG_ALLOC_ORDER. Comment before it says: " It is good to use
ip since no saving is required (though calls clobber it) and it never contains
function parameters. It is quite good to use lr since other calls may clobber
it anyway."
So in REG_ALLOC_ORDER, ip (reg 12) and lr (reg 14) come before before r4-r7:
#define REG_ALLOC_ORDER \
{ \
3, 2, 1, 0, 12, 14, 4, 5, \
6, 7, 8, 10, 9, 11, 13, 15, \
16, 17, 18, 19, 20, 21, 22, 23, \
27, 28, 29, 30, 31, 32, 33, 34, \
35, 36, 37, 38, 39, 40, 41, 42, \
43, 44, 45, 46, 47, 48, 49, 50, \
51, 52, 53, 54, 55, 56, 57, 58, \
59, 60, 61, 62, \
24, 25, 26, \
So the register allocator faithfully does what the IBTK has asked it to :-)
--
steven at gcc dot gnu dot org changed:
What|Removed |Added
GCC build triplet|i686-linux |
GCC host triplet|i686-linux |
Keywords|ra |
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #2 from ramana at gcc dot gnu dot org 2010-01-29 07:53 --- Confirmed - I'm marking this as an enhancement. -- ramana at gcc dot gnu dot org changed: What|Removed |Added Severity|normal |enhancement Status|UNCONFIRMED |NEW Ever Confirmed|0 |1 Keywords||missed-optimization, ra Last reconfirmed|-00-00 00:00:00 |2010-01-29 07:53:09 date|| http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
[Bug target/42895] Low registers are preferred than register ip in thumb2 mode
--- Comment #1 from carrot at google dot com 2010-01-29 00:14 --- Created an attachment (id=19744) --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=19744&action=view) test case -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42895
