[Bug target/49385] Invalid RTL intstruction for ARM
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49385 --- Comment #6 from jye2 at gcc dot gnu.org 2011-09-19 08:13:09 UTC --- Author: jye2 Date: Mon Sep 19 08:13:02 2011 New Revision: 178955 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=178955 Log: 2011-09-19 Jiangning Liu jiangning@arm.com Backport r175427 from mainline 2011-06-27 Richard Guenther rguent...@suse.de PR tree-optimization/49169 * fold-const.c (get_pointer_modulus_and_residue): Don't rely on the alignment of function decls. 2011-09-19 Jiangning Liu jiangning@arm.com Backport r175208 from mainline 2011-06-20 Ramana Radhakrishnan ramana.radhakrish...@linaro.org PR target/49385 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast one of the operands is a register. 2011-09-19 Jiangning Liu jiangning@arm.com Backport r174803 from mainline 2011-06-08 Julian Brown jul...@codesourcery.com * config/arm/arm.c (arm_libcall_uses_aapcs_base): Use correct ABI for double-precision helper functions in hard-float mode if only single-precision arithmetic is supported in hardware. Modified: branches/ARM/embedded-4_6-branch/gcc/ChangeLog.arm branches/ARM/embedded-4_6-branch/gcc/config/arm/arm.c branches/ARM/embedded-4_6-branch/gcc/config/arm/thumb2.md branches/ARM/embedded-4_6-branch/gcc/fold-const.c
[Bug target/49385] Invalid RTL intstruction for ARM
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49385 --- Comment #4 from Ramana Radhakrishnan ramana at gcc dot gnu.org 2011-06-20 12:16:04 UTC --- Author: ramana Date: Mon Jun 20 12:15:58 2011 New Revision: 175208 URL: http://gcc.gnu.org/viewcvs?root=gccview=revrev=175208 Log: Fix PR target/49385 2011-06-20 Ramana Radhakrishnan ramana.radhakrish...@linaro.org PR target/49385 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast one of the operands is a register. Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/thumb2.md
[Bug target/49385] Invalid RTL intstruction for ARM
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49385 Ramana Radhakrishnan ramana at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED CC||ramana at gcc dot gnu.org Resolution||FIXED Target Milestone|--- |4.7.0 --- Comment #5 from Ramana Radhakrishnan ramana at gcc dot gnu.org 2011-06-20 14:34:07 UTC --- Fixed now. ramana
[Bug target/49385] Invalid RTL intstruction for ARM
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49385 --- Comment #3 from revital.eres at linaro dot org 2011-06-15 11:26:32 UTC --- (In reply to comment #0) Created attachment 24504 [details] The test to reproduce the RTL instruction. I see the following invalid mem to mem RTL instruction in test2.c.189r.sched1 btw, the first dump file which contains this invalid mem-mem instruction is combine.
[Bug target/49385] Invalid RTL intstruction for ARM
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49385 --- Comment #1 from Mikael Pettersson mikpe at it dot uu.se 2011-06-13 11:20:23 UTC --- I get no ICE on this with 4.7 r174986, even with --enable-checking, and the assembler doesn't complain about the generated code. So what is the problem?
[Bug target/49385] Invalid RTL intstruction for ARM
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=49385 --- Comment #2 from revital.eres at linaro dot org 2011-06-13 11:26:44 UTC --- (In reply to comment #1) I get no ICE on this with 4.7 r174986, even with --enable-checking, and the assembler doesn't complain about the generated code. So what is the problem? The generated code does not produce ICE. However the RTL instruction is not valid as far as I understand so it should not be generated at any stage of the compilation.
