[Bug target/56484] [4.8 Regression] ICE in assign_by_spills, at lra-assigns.c:1268
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56484
--- Comment #7 from Jakub Jelinek jakub at gcc dot gnu.org 2013-03-05
11:06:26 UTC ---
Actually, looking more at this, I'd say combiner is innocent here, the problem
is earlier , during ce1 pass, which transforms:
16: ax:SI=call [`output_play'] argc:0
REG_DEAD di:DI
REG_DEAD si:SI
17: r60:SI=ax:SI
REG_DEAD ax:SI
18: flags:CCGOC=cmp(r59:SI,0)
19: pc={(flags:CCGOC=0)?L21:pc}
REG_DEAD flags:CCGOC
REG_BR_PROB 0x1c84
20: NOTE_INSN_BASIC_BLOCK 4
6: r60:SI=r59:SI
REG_DEAD r59:SI
21: L21:
22: NOTE_INSN_BASIC_BLOCK 5
into:
16: ax:SI=call [`output_play'] argc:0
REG_DEAD di:DI
REG_DEAD si:SI
17: r60:SI=ax:SI
REG_DEAD ax:SI
18: flags:CCGOC=cmp(r59:SI,0)
53: flags:CCGOC=cmp(r59:SI,0)
54: r60:SI={(flags:CCGOC=0)?ax:SI:r59:SI}
22: NOTE_INSN_BASIC_BLOCK 4
i.e. does what combiner tries to avoid with hard registers. I don't understand
why it can't use r60:SI instead of ax:SI.
[Bug target/56484] [4.8 Regression] ICE in assign_by_spills, at lra-assigns.c:1268
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56484 Jakub Jelinek jakub at gcc dot gnu.org changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed||2013-03-01 CC||jakub at gcc dot gnu.org, ||uros at gcc dot gnu.org Target Milestone|--- |4.8.0 Summary|ICE in assign_by_spills, at |[4.8 Regression] ICE in |lra-assigns.c:1268 |assign_by_spills, at ||lra-assigns.c:1268 Ever Confirmed|0 |1 --- Comment #4 from Jakub Jelinek jakub at gcc dot gnu.org 2013-03-01 08:30:31 UTC --- Started with http://gcc.gnu.org/viewcvs?root=gccview=revrev=188526 but it was merely latent before that, so it isn't LRA bug, because it fails with reload equally. I think the problem is in combine, where we have: ax = call ... flags = r59 != 0 r60 = flags = 0 ? ax : r59 r65 = buf r68 = 768 rep stosd [r65 .. r65 + r68 - 4] = 0 r59 = r60 and the combiner combines the r60 = flags = 0 ? ax : r59 instruction with r59 = r60 into r59 = flags = 0 ? ax : r59 instruction in the last spot, thus extending the lifetime of the ax and flags hard registers across various other instructions.
[Bug target/56484] [4.8 Regression] ICE in assign_by_spills, at lra-assigns.c:1268
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56484 --- Comment #5 from Venkataramanan venkataramanan.kumar at amd dot com 2013-03-01 08:42:42 UTC --- -fno-tree-coalesce-vars for workarround
[Bug target/56484] [4.8 Regression] ICE in assign_by_spills, at lra-assigns.c:1268
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56484 --- Comment #6 from Uros Bizjak ubizjak at gmail dot com 2013-03-01 18:06:28 UTC --- (In reply to comment #4) and the combiner combines the r60 = flags = 0 ? ax : r59 instruction with r59 = r60 into r59 = flags = 0 ? ax : r59 instruction in the last spot, thus extending the lifetime of the ax and flags hard registers across various other instructions. But AX is member of likely spilled class, so combine should take some more care with this insn. Should we just prevent propagations of all insns that mention likely spilled hard regs?
