[Bug target/59778] FAIL: gcc.dg/atomic/c11-atomic-exec-5.c

[danglin at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59778

John David Anglin  changed:

   What|Removed |Added

 Status|UNCONFIRMED |RESOLVED
 Resolution|--- |FIXED

--- Comment #6 from John David Anglin  ---
Fixed on trunk.

[Bug target/59778] FAIL: gcc.dg/atomic/c11-atomic-exec-5.c

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59778

--- Comment #5 from GCC Commits  ---
The master branch has been updated by John David Anglin :

https://gcc.gnu.org/g:266354012e0aa42e0d1639ee7708595f316cc36b

commit r14-8778-g266354012e0aa42e0d1639ee7708595f316cc36b
Author: John David Anglin 
Date:   Sat Feb 3 15:43:00 2024 +

libatomic: Provide FPU exception defines for __hppa__

The exception defines in  do not match the exception bits
in the FPU status register on hppa-linux and hppa64-hpux11.11.  On
linux, they match the trap enable bits.  On 64-bit hpux, they match
the exception bits for IA64.  The IA64 bits are in a different
order and location than HPPA.  HP uses table look ups to reorder
the bits in code to test and raise exceptions.

All the architectures that I looked at just pass the FPU status
register to __atomic_feraiseexcept().  The simplest approach for
hppa is to define FE_INEXACT, etc, to match the status register
and not include ..

2024-02-03  John David Anglin  

libatomic/ChangeLog:

PR target/59778
* configure.tgt (hppa*): Set ARCH.
* config/pa/fenv.c: New file.

[Bug target/59778] FAIL: gcc.dg/atomic/c11-atomic-exec-5.c

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59778

--- Comment #4 from GCC Commits  ---
The master branch has been updated by John David Anglin :

https://gcc.gnu.org/g:1c3cfb5a95dcc7f797ec2815690a6291878580c4

commit r14-8758-g1c3cfb5a95dcc7f797ec2815690a6291878580c4
Author: John David Anglin 
Date:   Fri Feb 2 18:05:06 2024 +

hppa: Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV

This change implements __builtin_get_fpsr() and __builtin_set_fpsr(x)
to get and set the floating-point status register.  They are used to
implement pa_atomic_assign_expand_fenv().

2024-02-02  John David Anglin  

gcc/ChangeLog:

PR target/59778
* config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
and PA_BUILTIN_SET_FPSR builtins.
* (pa_builtins_icode): Declare.
* (def_builtin, pa_fpu_init_builtins): New.
* (pa_init_builtins): Initialize FPU builtins.
* (pa_builtin_decl, pa_expand_builtin_1): New.
* (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
PA_BUILTIN_SET_FPSR builtins.
* (pa_atomic_assign_expand_fenv): New.
* config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
UNSPECV constants.
(get_fpsr, put_fpsr): New expanders.
(get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
insn patterns.

[Bug target/59778] FAIL: gcc.dg/atomic/c11-atomic-exec-5.c

[danglin at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59778

John David Anglin danglin at gcc dot gnu.org changed:

   What|Removed |Added

 Target|hppa-unknown-linux-gnu  |hppa*-*-*
   Host|hppa-unknown-linux-gnu  |hppa*-*-*
   Target Milestone|4.9.0   |---
  Build|hppa-unknown-linux-gnu  |hppa*-*-*

[Bug target/59778] FAIL: gcc.dg/atomic/c11-atomic-exec-5.c

[ro at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59778

Rainer Orth ro at gcc dot gnu.org changed:

   What|Removed |Added

 CC||ro at gcc dot gnu.org
   Target Milestone|--- |4.9.0

[Bug target/59778] FAIL: gcc.dg/atomic/c11-atomic-exec-5.c

[joseph at codesourcery dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59778

--- Comment #1 from joseph at codesourcery dot com joseph at codesourcery dot 
com ---
Please see the advice to architecture maintainers at 
http://gcc.gnu.org/ml/gcc/2013-11/msg00131.html.