[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #33 from Terry Guo terry.guo at arm dot com --- (In reply to clyon from comment #32) 2015-04-13 Terry Guo terry@arm.com PR target/65710 * gcc.target/arm/pr65710.c: New. Terry, any particular reason you use -march=armv6-m instead of -march=armv6 ? Some of my test configurations add -marm to RUNTESTFLAGS, and they fail because: error: target CPU does not support ARM mode Can we switch to armv6, or do we need a few additional guards to avoid running this test in unsupported configurations? Thanks for reminding. I just made a stupid copy-paste error here. The correct options should be -mthumb -O2 -mfloat-abi=soft as shown in comment#1. I reused some test case template and forgot to update the options. I will fix this soon.
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #32 from clyon at gcc dot gnu.org --- 2015-04-13 Terry Guo terry@arm.com PR target/65710 * gcc.target/arm/pr65710.c: New. Terry, any particular reason you use -march=armv6-m instead of -march=armv6 ? Some of my test configurations add -marm to RUNTESTFLAGS, and they fail because: error: target CPU does not support ARM mode Can we switch to armv6, or do we need a few additional guards to avoid running this test in unsupported configurations?
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #31 from xuepeng guo xguo at gcc dot gnu.org --- Author: xguo Date: Mon Apr 13 05:22:09 2015 New Revision: 222037 URL: https://gcc.gnu.org/viewcvs?rev=222037root=gccview=rev Log: Add missing test case 2015-04-13 Terry Guo terry@arm.com PR target/65710 * gcc.target/arm/pr65710.c: New. Added: trunk/gcc/testsuite/gcc.target/arm/pr65710.c Modified: trunk/gcc/testsuite/ChangeLog
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 Jakub Jelinek jakub at gcc dot gnu.org changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|--- |FIXED --- Comment #30 from Jakub Jelinek jakub at gcc dot gnu.org --- So hopefully fixed now.
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #26 from Vladimir Makarov vmakarov at gcc dot gnu.org --- Author: vmakarov Date: Fri Apr 10 19:43:28 2015 New Revision: 221984 URL: https://gcc.gnu.org/viewcvs?rev=221984root=gccview=rev Log: 2015-04-10 Vladimir Makarov vmaka...@redhat.com PR target/65710 * lra-assigns.c (spill_for): Update smallest_bad_spills_num. Print bad_spills_num and insn_pseudos_num. Modified: branches/gcc-4_9-branch/gcc/ChangeLog branches/gcc-4_9-branch/gcc/lra-assigns.c
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #27 from Vladimir Makarov vmakarov at gcc dot gnu.org --- (In reply to Stupachenko Evgeny from comment #16) I can't attach spec2000 benchmarks sources. The loop is in longest_match function in 164.gzip. Options to reproduce: -Ofast -funroll-loops -flto -march=corei7 -m32 -fPIE -pie (-march=slm reproduce the issue as well). I'm checking if the issue reproduced without -flto. Evgeny, could you check the effect of my latest patch (c25) on gzip.
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #28 from Yvan Roux yroux at gcc dot gnu.org --- (In reply to Vladimir Makarov from comment #25) Author: vmakarov Date: Fri Apr 10 19:38:55 2015 New Revision: 221983 URL: https://gcc.gnu.org/viewcvs?rev=221983root=gccview=rev Log: 2015-04-10 Vladimir Makarov vmaka...@redhat.com PR target/65710 * lra-assigns.c (spill_for): Update smallest_bad_spills_num. Print bad_spills_num and insn_pseudos_num. That indeed makes more sense than my workaround, I'm progressing in LRA but there is still way to go ! ;) Thanks Vlad
[Bug target/65710] [4.9/5 Regression] Thumb1 ICE caused by no register to spill
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=65710 --- Comment #29 from Stupachenko Evgeny evstupac at gmail dot com --- Evgeny, could you check the effect of my latest patch (c25) on gzip. The performance is back. Thanks.
