[Bug target/69617] PowerPC/e6500: Atomic byte/halfword operations not properly supported

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69617

Segher Boessenkool  changed:

   What|Removed |Added

 Status|UNCONFIRMED |NEW
   Last reconfirmed||2017-02-27
 CC||segher at gcc dot gnu.org
 Ever confirmed|0   |1

--- Comment #3 from Segher Boessenkool  ---
rs6000.h has

/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
   in power7, so conditionalize them on p8 features.  TImode syncs need quad
   memory support.  */
#define TARGET_SYNC_HI_QI   (TARGET_QUAD_MEMORY \
 || TARGET_QUAD_MEMORY_ATOMIC   \
 || TARGET_DIRECT_MOVE)

so someone needs to update this to work for the *500 cores as well.

[Bug target/69617] PowerPC/e6500: Atomic byte/halfword operations not properly supported

[sebastian.hu...@embedded-brains.de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69617

--- Comment #2 from Sebastian Huber  ---
Yes, sorry, I meant the load with reservation and store conditional
instructions.

[Bug target/69617] PowerPC/e6500: Atomic byte/halfword operations not properly supported

[scottwood at freescale dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69617

Scott wood  changed:

   What|Removed |Added

 CC||scottwood at freescale dot com

--- Comment #1 from Scott wood  ---
Decorated storage (lbdx and such) requires cache-inhibited memory, and the
operations are defined by each SoC rather than by the e6500 core -- this makes
it unusable by GCC.  The non-decorated l[bh]arx/st[bh]cx. could be used,
though.