[Bug target/71453] Spills to vector registers are sub-optimal.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71453 Hongtao.liu changed: What|Removed |Added CC||crazylht at gmail dot com --- Comment #7 from Hongtao.liu --- (In reply to CVS Commits from comment #6) > The master branch has been updated by hongtao Liu : > > https://gcc.gnu.org/g:00cb3494cab397b5655ab42fd69310883c12137c > > commit r11-2793-g00cb3494cab397b5655ab42fd69310883c12137c > Author: H.J. Lu > Date: Tue Sep 3 14:41:02 2019 -0700 > > x86: Add cost model for operation of mask registers. > > gcc/ > Just clarify that the whole patch set enable spilling to mask registers and has nothing to do with spill to vector registers.
[Bug target/71453] Spills to vector registers are sub-optimal.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71453 --- Comment #6 from CVS Commits --- The master branch has been updated by hongtao Liu : https://gcc.gnu.org/g:00cb3494cab397b5655ab42fd69310883c12137c commit r11-2793-g00cb3494cab397b5655ab42fd69310883c12137c Author: H.J. Lu Date: Tue Sep 3 14:41:02 2019 -0700 x86: Add cost model for operation of mask registers. gcc/ PR target/71453 * config/i386/i386.h (struct processor_costs): Add member mask_to_integer, integer_to_mask, mask_load[3], mask_store[3], mask_move. * config/i386/x86-tune-costs.h (ix86_size_cost, i386_cost, i386_cost, pentium_cost, lakemont_cost, pentiumpro_cost, geode_cost, k6_cost, athlon_cost, k8_cost, amdfam10_cost, bdver_cost, znver1_cost, znver2_cost, skylake_cost, btver1_cost, btver2_cost, pentium4_cost, nocona_cost, atom_cost, slm_cost, intel_cost, generic_cost, core_cost): Initialize mask_load[3], mask_store[3], mask_move, integer_to_mask, mask_to_integer for all target costs. * config/i386/i386.c (ix86_register_move_cost): Using cost model of mask registers. (inline_memory_move_cost): Ditto. (ix86_register_move_cost): Ditto.
[Bug target/71453] Spills to vector registers are sub-optimal.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71453 H.J. Lu changed: What|Removed |Added Status|SUSPENDED |NEW CC|izamyatin at gmail dot com |crazylht at gmail dot com, ||skpgkp2 at gmail dot com --- Comment #5 from H.J. Lu --- commit 0ccf1b9d72ec54742f14d0ded84fa34cb5a48e5b Author: uros Date: Wed Aug 28 15:09:51 2019 + diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index f3b3a9a326fd..d2d84eb11663 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18617,9 +18617,9 @@ ix86_register_move_cost (machine_mode mode, reg_class_t class1_i, where integer modes in SSE registers are not tieable because of missing QImode and HImode moves to, from or between MMX/SSE registers. */ -return MAX (8, SSE_CLASS_P (class1) - ? ix86_cost->hard_register.sse_to_integer - : ix86_cost->hard_register.integer_to_sse); +return (SSE_CLASS_P (class1) + ? ix86_cost->hard_register.sse_to_integer + : ix86_cost->hard_register.integer_to_sse); if (MAYBE_FLOAT_CLASS_P (class1)) return ix86_cost->hard_register.fp_move; removed the cost floor on inter-unit moves. It results in spills to vector registers.
[Bug target/71453] Spills to vector registers are sub-optimal.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71453 Uroš Bizjak changed: What|Removed |Added Status|UNCONFIRMED |SUSPENDED Last reconfirmed||2016-06-26 Ever confirmed|0 |1 --- Comment #4 from Uroš Bizjak --- Suspended until the infrastructure is ready.
[Bug target/71453] Spills to vector registers are sub-optimal.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71453 --- Comment #3 from uros at gcc dot gnu.org --- Author: uros Date: Sun Jun 26 20:56:34 2016 New Revision: 237792 URL: https://gcc.gnu.org/viewcvs?rev=237792=gcc=rev Log: PR target/70902 PR target/71453 PR target/71555 PR target/71596 PR target/71657 * config/i386/i386.c (TARGET_SPILL_CLASS): #if 0 out the definition. (ix86_spill_class): Disable to always return NO_REGS. Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386.c
