[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #16 from ro at CeBiTec dot Uni-Bielefeld.DE --- > This shouldn't happen with degagnu after > > http://git.savannah.gnu.org/gitweb/?p=dejagnu.git;a=commit;h=5256bd82343000c76bc0e48139003f90b6184347 Which would mean requiring at least DejaGnu 1.6, while install.texi still states a minimum of 1.4.4. The other issue (unconditionally generating .code16gcc without checking if the assembler supports it) still stands. Rainer
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #15 from H.J. Lu --- > > Could be a bug in the old Apple as. However, the testcase is fishy in > explicitly passing -m16. For multilibbed x86 targets, that gets > overridden for the non-default multilibs (either with -m32 or m64). This shouldn't happen with degagnu after http://git.savannah.gnu.org/gitweb/?p=dejagnu.git;a=commit;h=5256bd82343000c76bc0e48139003f90b6184347
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #14 from ro at CeBiTec dot Uni-Bielefeld.DE --- >> /var/folders/zz/zyxvpxvq6csfxvn_n87r00021y/T//cchNxmiW.s:7:no such >> instruction: `shrx %eax, 4(%esp),%eax' > http://www.felixcloutier.com/x86/SARX:SHLX:SHRX.html Could be a bug in the old Apple as. However, the testcase is fishy in explicitly passing -m16. For multilibbed x86 targets, that gets overridden for the non-default multilibs (either with -m32 or m64).
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #13 from Uroš Bizjak --- (In reply to r...@cebitec.uni-bielefeld.de from comment #12) > I've just checked a x86_64-apple-darwin11.4.2 build: the test PASSes for > -m64, but FAILs for -m32 with > > /var/folders/zz/zyxvpxvq6csfxvn_n87r00021y/T//cchNxmiW.s:7:no such > instruction: `shrx %eax, 4(%esp),%eax' http://www.felixcloutier.com/x86/SARX:SHLX:SHRX.html
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #12 from ro at CeBiTec dot Uni-Bielefeld.DE --- I've just checked a x86_64-apple-darwin11.4.2 build: the test PASSes for -m64, but FAILs for -m32 with /var/folders/zz/zyxvpxvq6csfxvn_n87r00021y/T//cchNxmiW.s:7:no such instruction: `shrx %eax, 4(%esp),%eax'
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #11 from ro at CeBiTec dot Uni-Bielefeld.DE --- The problem still exists, and according to gcc-testresults the test FAILs on i386-pc-solaris2.11, x86_64-pc-solaris2.11, x86_64-apple-darwin15.6.0, i686-pc-linux-gnu, and x86_64-pc-linux-gnu. Should I rather open a new PR for this? Rainer
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 Rainer Orth changed: What|Removed |Added CC||ro at gcc dot gnu.org --- Comment #10 from Rainer Orth --- There are some problems with the testcase: * Solaris/x86 with /bin/as, I get FAIL: gcc.target/i386/pr80569.c (test for excess errors) Excess errors: Assembler: pr80569.c "/var/tmp//ccB_4KXd.s", line 2 : Illegal mnemonic Near line: ".code16gcc" "/var/tmp//ccB_4KXd.s", line 2 : Syntax error Near line: ".code16gcc" i386.c (x86_file_start) unconditionally emits .code16gcc without any check that the assembler supports it. * on Linux/i686, I get Excess errors: /vol/gcc/src/hg/trunk/local/gcc/testsuite/gcc.target/i386/pr80569.c:7:24: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] new from gcc is called with-m16 -march=haswell -c -m64 Rainer
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 Uroš Bizjak changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED Target Milestone|--- |5.5 --- Comment #9 from Uroš Bizjak --- Fixed everywhere.
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #8 from uros at gcc dot gnu.org --- Author: uros Date: Mon Jul 24 20:29:02 2017 New Revision: 250486 URL: https://gcc.gnu.org/viewcvs?rev=250486=gcc=rev Log: PR target/80569 * config/i386/i386.c (ix86_option_override_internal): Disable BMI, BMI2 and TBM instructions for -m16. testsuite/ChangeLog: PR target/80569 * gcc.target/i386/pr80569.c: New test. Added: branches/gcc-5-branch/gcc/testsuite/gcc.target/i386/pr80569.c Modified: branches/gcc-5-branch/gcc/ChangeLog branches/gcc-5-branch/gcc/config/i386/i386.c branches/gcc-5-branch/gcc/testsuite/ChangeLog
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #7 from uros at gcc dot gnu.org --- Author: uros Date: Mon Jul 24 18:59:21 2017 New Revision: 250479 URL: https://gcc.gnu.org/viewcvs?rev=250479=gcc=rev Log: PR target/80569 * config/i386/i386.c (ix86_option_override_internal): Disable BMI, BMI2 and TBM instructions for -m16. testsuite/ChangeLog: PR target/80569 * gcc.target/i386/pr80569.c: New test. Added: branches/gcc-6-branch/gcc/testsuite/gcc.target/i386/pr80569.c Modified: branches/gcc-6-branch/gcc/ChangeLog branches/gcc-6-branch/gcc/config/i386/i386.c branches/gcc-6-branch/gcc/testsuite/ChangeLog
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #6 from uros at gcc dot gnu.org --- Author: uros Date: Sun Jul 23 10:33:08 2017 New Revision: 250460 URL: https://gcc.gnu.org/viewcvs?rev=250460=gcc=rev Log: PR target/80569 * config/i386/i386.c (ix86_option_override_internal): Disable BMI, BMI2 and TBM instructions for -m16. testsuite/ChangeLog: PR target/80569 * gcc.target/i386/pr80569.c: New test. Added: branches/gcc-7-branch/gcc/testsuite/gcc.target/i386/pr80569.c Modified: branches/gcc-7-branch/gcc/ChangeLog branches/gcc-7-branch/gcc/config/i386/i386.c branches/gcc-7-branch/gcc/testsuite/ChangeLog
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #5 from uros at gcc dot gnu.org --- Author: uros Date: Sun Jul 23 10:28:26 2017 New Revision: 250459 URL: https://gcc.gnu.org/viewcvs?rev=250459=gcc=rev Log: PR target/80569 * config/i386/i386.c (ix86_option_override_internal): Disable BMI, BMI2 and TBM instructions for -m16. testsuite/ChangeLog: PR target/80569 * gcc.target/i386/pr80569.c: New test. Added: trunk/gcc/testsuite/gcc.target/i386/pr80569.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386.c trunk/gcc/testsuite/ChangeLog
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #4 from Davin McCall --- (In reply to Uroš Bizjak from comment #3) > Can you please test attached patch? That seems to fix the problem, yes. Thanks.
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #3 from Uroš Bizjak --- Created attachment 41810 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=41810=edit Proposed patch Can you please test attached patch?
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #2 from Davin McCall --- Still happening in 7.1. -march=core2 suppresses, generation of the problematic instruction happens with -march=haswell.
[Bug target/80569] i686: "shrx" instruction generated in 16-bit mode
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80569 --- Comment #1 from Davin McCall --- (Prevents building Qemu).
