[Bug target/82483] ICE on invalid use w/ -mno-mmx

2017-10-10 Thread jakub at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82483

Jakub Jelinek  changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Jakub Jelinek  ---
Fixed on the trunk.

[Bug target/82483] ICE on invalid use w/ -mno-mmx

2017-10-10 Thread jakub at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82483

--- Comment #3 from Jakub Jelinek  ---
Author: jakub
Date: Tue Oct 10 20:06:33 2017
New Revision: 253609

URL: https://gcc.gnu.org/viewcvs?rev=253609=gcc=rev
Log:
PR target/79565
PR target/82483
* config/i386/i386.c (ix86_init_mmx_sse_builtins): Add
OPTION_MASK_ISA_MMX for __builtin_ia32_maskmovq,
__builtin_ia32_vec_ext_v4hi and __builtin_ia32_vec_set_v4hi.
(ix86_expand_builtin): Treat OPTION_MASK_ISA_MMX similarly
to OPTION_MASK_ISA_AVX512VL - builtins that have both
OPTION_MASK_ISA_MMX and some other bit set require both
mmx and the ISAs without the mmx bit.
* config/i386/i386-builtin.def (__builtin_ia32_cvtps2pi,
__builtin_ia32_cvttps2pi, __builtin_ia32_cvtpi2ps,
__builtin_ia32_pavgb, __builtin_ia32_pavgw, __builtin_ia32_pmulhuw,
__builtin_ia32_pmaxub, __builtin_ia32_pmaxsw, __builtin_ia32_pminub,
__builtin_ia32_pminsw, __builtin_ia32_psadbw, __builtin_ia32_pmovmskb,
__builtin_ia32_pshufw, __builtin_ia32_cvtpd2pi,
__builtin_ia32_cvttpd2pi, __builtin_ia32_cvtpi2pd,
__builtin_ia32_pmuludq, __builtin_ia32_pabsb, __builtin_ia32_pabsw,
__builtin_ia32_pabsd, __builtin_ia32_phaddw, __builtin_ia32_phaddd,
__builtin_ia32_phaddsw, __builtin_ia32_phsubw, __builtin_ia32_phsubd,
__builtin_ia32_phsubsw, __builtin_ia32_pmaddubsw,
__builtin_ia32_pmulhrsw, __builtin_ia32_pshufb, __builtin_ia32_psignb,
__builtin_ia32_psignw, __builtin_ia32_psignd, __builtin_ia32_movntq,
__builtin_ia32_paddq, __builtin_ia32_psubq, __builtin_ia32_palignr):
Add OPTION_MASK_ISA_MMX.

* gcc.target/i386/pr82483-1.c: New test.
* gcc.target/i386/pr82483-2.c: New test.

Added:
trunk/gcc/testsuite/gcc.target/i386/pr82483-1.c
trunk/gcc/testsuite/gcc.target/i386/pr82483-2.c
Modified:
trunk/gcc/ChangeLog
trunk/gcc/config/i386/i386-builtin.def
trunk/gcc/config/i386/i386.c
trunk/gcc/testsuite/ChangeLog

[Bug target/82483] ICE on invalid use w/ -mno-mmx

2017-10-09 Thread jakub at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82483

Jakub Jelinek  changed:

   What|Removed |Added

 Status|UNCONFIRMED |ASSIGNED
   Last reconfirmed||2017-10-09
   Assignee|unassigned at gcc dot gnu.org  |jakub at gcc dot gnu.org
 Ever confirmed|0   |1

--- Comment #2 from Jakub Jelinek  ---
Created attachment 42327
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=42327=edit
gcc8-pr82483.patch

Untested fix.

[Bug target/82483] ICE on invalid use w/ -mno-mmx

2017-10-09 Thread jakub at gcc dot gnu.org 
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82483

--- Comment #1 from Jakub Jelinek  ---
More complete testcase, all of these ICE individually (except f19) with -mssse3
-mno-mmx:

#include 

void f1 (__m64 x, __m64 y, char *z) { _mm_maskmove_si64 (x, y, z); }
int f2 (__m64 x) { return _mm_extract_pi16 (x, 1); }
__m64 f3 (__m64 x, int y) { return _mm_insert_pi16 (x, y, 1); }
__m64 f4 (__m128 x) { return _mm_cvtps_pi32 (x); }
__m64 f5 (__m128 x) { return _mm_cvttps_pi32 (x); }
__m128 f6 (__m128 x, __m64 y) { return _mm_cvtpi32_ps (x, y); }
__m64 f7 (__m64 x, __m64 y) { return _mm_avg_pu8 (x, y); }
__m64 f8 (__m64 x, __m64 y) { return _mm_avg_pu16 (x, y); }
__m64 f9 (__m64 x, __m64 y) { return _mm_mulhi_pu16 (x, y); }
__m64 f10 (__m64 x, __m64 y) { return _mm_max_pu8 (x, y); }
__m64 f11 (__m64 x, __m64 y) { return _mm_max_pi16 (x, y); }
__m64 f12 (__m64 x, __m64 y) { return _mm_min_pu8 (x, y); }
__m64 f13 (__m64 x, __m64 y) { return _mm_min_pi16 (x, y); }
__m64 f14 (__m64 x, __m64 y) { return _mm_sad_pu8 (x, y); }
int f15 (__m64 x) { return _mm_movemask_pi8 (x); }
__m64 f16 (__m64 x) { return _mm_shuffle_pi16 (x, 1); }
__m64 f17 (__m128d x) { return _mm_cvtpd_pi32 (x); }
__m64 f18 (__m128d x) { return _mm_cvttpd_pi32 (x); }
__m128d f19 (__m64 x) { return _mm_cvtpi32_pd (x); }
__m64 f20 (__m64 x, __m64 y) { return _mm_mul_su32 (x, y); }
__m64 f21 (__m64 x) { return _mm_abs_pi8 (x); }
__m64 f22 (__m64 x) { return _mm_abs_pi16 (x); }
__m64 f23 (__m64 x) { return _mm_abs_pi32 (x); }
__m64 f24 (__m64 x, __m64 y) { return _mm_hadd_pi16 (x, y); }
__m64 f25 (__m64 x, __m64 y) { return _mm_hadd_pi32 (x, y); }
__m64 f26 (__m64 x, __m64 y) { return _mm_hadds_pi16 (x, y); }
__m64 f27 (__m64 x, __m64 y) { return _mm_hsub_pi16 (x, y); }
__m64 f28 (__m64 x, __m64 y) { return _mm_hsub_pi32 (x, y); }
__m64 f29 (__m64 x, __m64 y) { return _mm_hsubs_pi16 (x, y); }
__m64 f30 (__m64 x, __m64 y) { return _mm_maddubs_pi16 (x, y); }
__m64 f31 (__m64 x, __m64 y) { return _mm_mulhrs_pi16 (x, y); }
__m64 f32 (__m64 x, __m64 y) { return _mm_shuffle_pi8 (x, y); }
__m64 f33 (__m64 x, __m64 y) { return _mm_sign_pi8 (x, y); }
__m64 f34 (__m64 x, __m64 y) { return _mm_sign_pi16 (x, y); }
__m64 f35 (__m64 x, __m64 y) { return _mm_sign_pi32 (x, y); }

These are all SSE or SSE2 or SSSE3 instructions don't require MMX CPUID, but
actually have (or in case of f6/f19 might have, the input allows memory operand
too; note f6 still ICEs though) MMX register operand(s), so with -mno-mmx can't
really work, as ix86_vector_mode_supported_p will return false for the
V2SI/V4HI/V8QImode.

I think easiest would be to require both {SSE/SSE2/SSSE3} and MMX ISAs for
these, turning a -mno-mmx switch into a hard request to never use %mm0-%mm7
registers for anything.