[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 Richard Earnshaw changed: What|Removed |Added Target Milestone|--- |6.5
[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 Renlin Li changed: What|Removed |Added Status|REOPENED|RESOLVED Resolution|--- |FIXED --- Comment #6 from Renlin Li --- (In reply to Richard Earnshaw from comment #3) > Doesn't this need backporting? Yes, it is needed. The same problem happens in gcc-6 and gcc-7. The backporting is approved and committed now.
[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 --- Comment #5 from Renlin Li --- Author: renlin Date: Thu Feb 1 21:33:05 2018 New Revision: 257315 URL: https://gcc.gnu.org/viewcvs?rev=257315=gcc=rev Log: [PR83370][AARCH64]Use tighter register constraint for sibcall patterns. gcc/ backport from mainline 2018-02-01 Renlin LiPR target/83370 * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle TAILCALL_ADDR_REGS. (aarch64_register_move_cost): Likewise. * config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. Remove IP registers. * config/aarch64/aarch64.md (Ucs): Update register constraint. gcc/testsuite/ backport from mainline 2018-02-01 Richard Sandiford PR target/83370 * gcc.target/aarch64/pr83370.c: New. Added: branches/gcc-6-branch/gcc/testsuite/gcc.target/aarch64/pr83370.c Modified: branches/gcc-6-branch/gcc/ChangeLog branches/gcc-6-branch/gcc/config/aarch64/aarch64.c branches/gcc-6-branch/gcc/config/aarch64/aarch64.h branches/gcc-6-branch/gcc/config/aarch64/constraints.md branches/gcc-6-branch/gcc/testsuite/ChangeLog
[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 --- Comment #4 from Renlin Li --- Author: renlin Date: Thu Feb 1 21:09:06 2018 New Revision: 257314 URL: https://gcc.gnu.org/viewcvs?rev=257314=gcc=rev Log: [PR83370][AARCH64]Use tighter register constraint for sibcall patterns. gcc/ backport from mainline 2018-02-01 Renlin LiPR target/83370 * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle TAILCALL_ADDR_REGS. (aarch64_register_move_cost): Likewise. * config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. Remove IP registers. * config/aarch64/aarch64.md (Ucs): Update register constraint. gcc/testsuite/ backport from mainline 2018-02-01 Richard Sandiford PR target/83370 * gcc.target/aarch64/pr83370.c: New. Added: branches/gcc-7-branch/gcc/testsuite/gcc.target/aarch64/pr83370.c Modified: branches/gcc-7-branch/gcc/ChangeLog branches/gcc-7-branch/gcc/config/aarch64/aarch64.c branches/gcc-7-branch/gcc/config/aarch64/aarch64.h branches/gcc-7-branch/gcc/config/aarch64/constraints.md branches/gcc-7-branch/gcc/testsuite/ChangeLog
[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 Richard Earnshaw changed: What|Removed |Added Status|RESOLVED|REOPENED Last reconfirmed||2018-02-01 CC||renlin.li at arm dot com Resolution|FIXED |--- Ever confirmed|0 |1 --- Comment #3 from Richard Earnshaw --- Doesn't this need backporting?
[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 Renlin Li changed: What|Removed |Added Status|UNCONFIRMED |RESOLVED Resolution|--- |FIXED --- Comment #2 from Renlin Li --- fix has been commit in trunk.
[Bug target/83370] [AARCH64]Tailcall register may be corrupted by epilogue code
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83370 --- Comment #1 from Renlin Li --- Author: renlin Date: Thu Feb 1 13:02:24 2018 New Revision: 257294 URL: https://gcc.gnu.org/viewcvs?rev=257294=gcc=rev Log: [PR83370][AARCH64]Use tighter register constraint for sibcall patterns. In aarch64 backend, ip0/ip1 register will be used in the prologue/epilogue as temporary register. When the compiler is performing sibcall optimization. It has the chance to use ip0/ip1 register for indirect function call to hold the address. However, those two register might be clobbered by the epilogue code which makes the last sibcall instruction invalid. The patch here renames the register class CALLER_SAVE_REGS to TAILCALL_ADDR_REGS to reflect its usage, and remove IP registers from this class. gcc/ 2018-02-01 Renlin LiPR target/83370 * config/aarch64/aarch64.c (aarch64_class_max_nregs): Handle TAILCALL_ADDR_REGS. (aarch64_register_move_cost): Likewise. * config/aarch64/aarch64.h (reg_class): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Rename CALLER_SAVE_REGS to TAILCALL_ADDR_REGS. Remove IP registers. * config/aarch64/aarch64.md (Ucs): Update register constraint. gcc/testsuite/ 2018-02-01 Richard Sandiford PR target/83370 * gcc.target/aarch64/pr83370.c: New. Added: trunk/gcc/testsuite/gcc.target/aarch64/pr83370.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/aarch64/aarch64.c trunk/gcc/config/aarch64/aarch64.h trunk/gcc/config/aarch64/constraints.md trunk/gcc/testsuite/ChangeLog